PIC18F442-I/PT Microchip Technology, PIC18F442-I/PT Datasheet - Page 223

• Manufacturer Part Number: PIC18F442-I/PT
• Description: IC MCU FLASH 8KX16 EE A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F442-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

BNC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Carry
If Carry
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Carry
[ label ] BNC
-128
if carry bit is ’0’
(PC) + 2 + 2n
None
If the Carry bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
'n'
'n'
=
=
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
127
0011
BNC
operation
Process
Process
Data
Data
No
Q3
Q3
n
PC
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
BNN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Negative
If Negative
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Negative
[ label ] BNN
-128
if negative bit is ’0’
(PC) + 2 + 2n
None
If the Negative bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
'n'
'n'
=
=
=
=
=
PIC18FXX2
n
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
127
0111
BNN
operation
Process
Process
Data
Data
No
Q3
Q3
n
DS39564C-page 221
PC
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn