nb7vpq16m ON Semiconductor, nb7vpq16m Datasheet

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nb7vpq16m

Manufacturer Part Number
nb7vpq16m
Description
1.8v / 2.5v Cml 12.5 Gbps Programmable Pre-emphasis Copper/cable Driver With Selectable Equalizer Receiver
Manufacturer
ON Semiconductor
Datasheet

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NB7VPQ16M
1.8V / 2.5V CML 12.5 Gbps Programmable
Pre-Emphasis Copper/Cable Driver with
Selectable Equalizer Receiver
Multi-Level Inputs w/ Internal Termination
Description
Pre-Emphasis CML Driver with an Equalizer Receiver (signal enhancer) that
operates up to 12.5Gbps with a 1.8V or 2.5V power supply. When placed in
series with a Data/Clock path, the NB7VPQ16M inputs will compensate the
degraded signal transmitted across a FR4 PCB backplane or cable interconnect.
Therefore, the serial data rate is increased by reducing Inter-Symbol Interference
(ISI) caused by losses in copper interconnect or long cables.
and SCLKIN (Serial Clock In) control inputs and contains circuitry which provides
sixteen programmable Pre-Emphasis settings to select the optimal output compensation level.
These selectable output levels will handle various backplane lengths and cable lines.
The first four SDIN bits (D3:D0) will digitally select 0 dB through 12 dB typical of
de-emphasis (see Table 1).
For cascaded applications, the shifted SDIN and SCLKIN signals are presented at
the SDOUT and SCLKOUT pins.
The 5
of the receiver.
resistors, in a 100- Ω center-tapped configuration, via the VT pin and will accept
LVPECL, CML or LVDS logic levels. This feature provides transmission line
termination on-chip, at the receiver end, eliminating external components.
performance Data/Clock products with Pre-Emphasis/Equalization (PEEQ).
Features
• Maximum Input Data Rate > 12.5Gbps
• Maximum Input Clock Frequency > 8GHz
• Drives Up To 18-inches of FR4
• (16) Programmable Output De-emphasis Levels; 0dB through 12dB
• 100ps typical Propagation Delay
• Differential CML Outputs, 400mV peak-to-peak, typical (PE = 0dB)
• Operating Range: V
• Internal Output Termination Resistors, 50-Ω
• QFN-16 Package, 3mm x 3mm, Pb-free
• -40ºC to +85ºC Ambient Operating Temperature
© Semiconductor Components Industries, LLC, 2003
The Pre-Emphasis buffer is controlled using a serial bus via the SDIN (Serial Data In)
The NB7VPQ16M is a high performance single channel programmable
The differential Data / Clock inputs incorporate a pair of internal 50-Ω termination
The NB7VPQ16M is a member of the GigaComm™ family of high
th
-bit (LSB) of the serial data bits allows for enabling the equalization function
CC
= 1.71V to 2.625V, GND = 0V
1
INb
VT
IN
EQ
Figure 1. Simplified Logic Diagram
http://onsemi.com
0
1
Publication Order Number:
SDIN
SCLKIN
SLOAD
NB7VPQ16M/D
1
16
PE
DAC
SDI
NB7V
PQ16M
ALYW
Rev. 9-29-08
SDOUT
SCLKOUT
Q
Qb

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nb7vpq16m Summary of contents

Page 1

... VT pin and will accept LVPECL, CML or LVDS logic levels. This feature provides transmission line termination on-chip, at the receiver end, eliminating external components. The NB7VPQ16M is a member of the GigaComm™ family of high performance Data/Clock products with Pre-Emphasis/Equalization (PEEQ). Features • ...

Page 2

... IN / INb Inputs By-pass the Equalizer section 1 Inputs flow through the Equalizer NB7VPQ16M SDIN (15) SCLKIN (14) SLOAD (13) EQEN (Equalizer Enable) 0 2:1 Mux EQ 1 Limiting Amp Figure 2. Detailed Block Diagram of NB7VPQ16M PE Output VODPE Q Low (mV) Qb High typical Default 435 Bit n -1 -1.0 dB 390 -1.5 dB 365 -2.0 dB 345 -2 ...

Page 3

... INb 3 GND 4 Figure 4. NB7VPQ16M Pinout: QFN-16 (Top View) Table3. Pin Description Pin Name I LVPECL, CML LVDS Input LVPECL, CML, 3 INb LVDS Input 4 GND - 5 VCCD - 6 SDOUT LVCMOS Output 7 SCLKOUT LVCMOS Output 8 GND - 9 VCC - 10 Qb CML 11 Q CML 12 VCC ...

Page 4

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. NB7VPQ16M Value > 4kV > 200 V 75kΩ ...

Page 5

... V – 500 V – 400 CC CC 2000 2100 mV V – 450 V –350 CC CC 1350 1450 100 mV CC 1200 mV 20 150 uA 5 150 CCD V x 0.35 mV CCD 20 150 uA 5 150 uA VCC mV 200 mV Ω Ω Publication Order Number: NB7VPQ16M/D ...

Page 6

... max varies 1:1 with V CMR EE CMR input signal. 12. Additive RMS jitter with 50% duty cycle Clock signal. 13. Peak-to-Peak jitter with input NRZ data at PRBS23. NB7VPQ16M 1.71V to 2.625V; GND = 0V -40°C to 85°C (Note 9) CC CCD Min 12.5 VOUTPP ≥ 200mV ...

Page 7

... ILDmax VINPP V IHDtyp V ILDtyp V IHDmin V ILDmin t H1 SLOAD min Figure 11. SLOAD Set-Up and Hold and t pw http://onsemi.com 7 VCC 50−Ω 50−Ω 50-Ω 50-Ω VEE IN SCLKIN min PW min pw Publication Order Number: NB7VPQ16M/D IN ...

Page 8

... Data Inputs The differential IN/INb inputs of the NB7VPQ16M can accept LVPECL, CML, and LVDS signal levels. The limitations for a differential input signal (LVDS, LVPECL, or CML minimum input swing of 100 mV (single-ended measurement). Within this condition, the input HIGH voltage, VIH, can range from V interfaces are illustrated in Figure 18 ...

Page 9

... VCC is required. See Figure 19 for output termination scheme. Power Supply Bypass information A clean power supply will optimize the performance of the NB7VPQ16M. The device provides VCC power supply pins for the digital circuitry and CML outputs. Placing a 0.01uF to 0.1uF bypass capacitor on each VCC pin to ground will help ensure a noise free VCC power supply ...

Page 10

... When SLOAD is brought LOW, the PE shift registers of all devices are enabled and data is written into the NB7VPQ16Ms with the contents of the PE shift registers. When the data transfer is complete, SLOAD is brought HIGH and all NB7VPQ16Ms are updated simultaneously. After the PE control bits are clocked into their appropriate registers, the Low-to-High transition of SLOAD will latch the data bits for the Pre-Emphasis DACs ...

Page 11

... NB7VPQ16M Pre-emphasis Driver Q Qb Figure 16. Typical NB7VPQ16M PreEmphasis Application at 6.5Gbps - Jitter Measurement Points, without and with pre-emphasis. NB7VPQ16M EQEN = 0 Pre-emphasis Driver PE = 0dB DJ1 NB7VPQ16M Output PE = 0dB Figure 17. Typical NB7VPQ16M Equalizer Application and Interconnect with the NB7VPQ16M; PRBS23 pattern at 6.5Gbps NB7VPQ16M = 12” Backplane FR4 ≤ ...

Page 12

... Db GND VCC VCC Single- 50Ω ended Driver 50Ω GND GND Figure __. Capacitor-Coupled Single-Ended Interface (VT connected to external http://onsemi.com 12 VCC NB7V16Q1 NB7VPQ16M Zo = 50Ω 50Ω Open Zo = 50Ω 50Ω INb Db GND VCC NB7V16Q1 NB7VPQ16M Zo = 50Ω 50Ω VREFAC* 50Ω ...

Page 13

... Q Qb 16mA GND Figure 19. Typical CML Output Structure and Termination 21. ORDERING INFORMATION Device NB7VPQ16MMNG NB7VPQ16MMNTXG NB7VPQ16M Receiver NB7VPQ16M VCCO VCC (Receiver) 50-Ω 50-Ω Figure 20. Alternative Output Termination VCC IN INb Package QFN-16 (Pb-free) QFN-16 (Pb-free) http://onsemi.com 13 Receiver 50-Ω ...

Page 14

... NB7VPQ16M http://onsemi.com 14 ...

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