nb7vpq16m ON Semiconductor, nb7vpq16m Datasheet - Page 8

• Manufacturer Part Number: nb7vpq16m
• Description: 1.8v / 2.5v Cml 12.5 Gbps Programmable Pre-emphasis Copper/cable Driver With Selectable Equalizer Receiver
• Manufacturer: ON Semiconductor

Data Inputs
limitations for a differential input signal (LVDS, LVPECL, or CML) is a minimum input swing of 100 mV (single-ended
measurement). Within this condition, the input HIGH voltage, VIH, can range from V
interfaces are illustrated in Figure 18.
Serial Data Interface
The Serial Data Interface (SDI) logic is implemented with a 5-bit shift register scheme. The register shifts once per rising
edge of the SCLKIN input. The serial data input SDIN must meet setup and hold timing as specified in the AC table. The
configuration latches will capture the value of the shift register on the Low-to-High edge of the SLOAD input. The most
significant bit (MSB) is loaded first. See the programming timing diagram for more information.
SDIN / SCLKIN
SDIN is the Serial Data input pin; SCLKIN is the Serial Clock input pin.
SLOAD
The SLOAD pin performs the DAC latch function. When LOW or left open, the DAC latch will pass the shift register
outputs to the input of the DAC and the EQualizer ENable bit (EQEN). On the Low-to-HIGH transition of SLOAD, the
input to the 4-bit DAC is locked to the state prior to when SLOAD went HIGH, and will set the EQualizer ENable bit. The
DAC does not get programmed until SLOAD goes HIGH. The SLOAD pin must remain in a HIGH state to maintain the
DAC Pre-Emphasis and the EQEN settings. A LOW or open state resets the DAC to 0db Pre-Emphasis setting and
disables the EQEN bit, regardless of SDIN and SCLKIN values. The SLOAD function is asynchronous.
Pre-Emphasis Selection
control inputs and contains circuitry which provides sixteen programmable pre-emphasis levels to control the output
compensation. The 4-bits (D3:D0) digitally select 0 dB through 12 dB of Pre-Emphasis compensation (see Table 1). The
default state at start-up is PE = 0dB.
EQualization ENable (EQEN)
realized by setting the 5
the Equalizer. When EQEN is set High, the IN/INb inputs flow through the Equalizer. The default state at start-up is
EQEN = LOW.
SLOAD
The Pre-Emphasis buffer is controlled using a serial bus via the SDIN (Serial Data In) and SCLKIN (Serial Clock In)
The EQualizer ENable (EQEN) allows for enabling the Equalizer function. The control of the Equalizer function is
The differential IN/INb inputs of the NB7VPQ16M can accept LVPECL, CML, and LVDS signal levels. The
SCLKOUT
Figure 12. Timing Diagram for Single Channel
SDIN
SCLKIN
SDOUT
D3
1
/////
th
D2
1
bit, EQEN, of the 5-bit serial data. When EQEN is set Low (or open), the IN/INb inputs bypass
2
/////
5 Clocks
2
D1
3
/////
t
PW
D0
3
min
4
Application Information
/////
EQEN /////
4
5
http://onsemi.com
NB7VPQ16M
D3
SCLKIN to SDOUT
5
6
8
D2
/////
6
7
D1
/////
7
8
D0
/////
8
9
EQEN /////
CC
9
/////
down to 1.1 V. Example
10
10
//////
11
/////
11
//////
12
/////