nb7vpq16m ON Semiconductor, nb7vpq16m Datasheet - Page 9

• Manufacturer Part Number: nb7vpq16m
• Description: 1.8v / 2.5v Cml 12.5 Gbps Programmable Pre-emphasis Copper/cable Driver With Selectable Equalizer Receiver
• Manufacturer: ON Semiconductor

D3
1
Q / Qb Outputs
outputs are designed to drive differential transmission lines with nominal 50-Ω characteristic impedance. External
termination with a 50-ohm resistor to VCC is required. See Figure 19 for output termination scheme.
Power Supply Bypass information
the digital circuitry and CML outputs. Placing a 0.01uF to 0.1uF bypass capacitor on each VCC pin to ground will help ensure a
noise free VCC power supply. The purpose of this design technique is to isolate the CMOS digital switching noise from the
high speed input/output path.
Cascade Application
SDOUT / SCLKOUT
shift register and will produce the SDIN / SCLKIN signals after five serial clock cycles, see Figure 13. The purpose of
SDOUT and SCLKOUT is for use in cascade applications, described below.
The differential output buffers of the NB7VPQ16M, Q and Qb, utilize Common Mode Logic (CML) architecture. The
A clean power supply will optimize the performance of the NB7VPQ16M. The device provides VCC power supply pins for
SDOUT is the Serial Data output pin; SCLKOUT is the Serial Clock output pin. These pins are the outputs of the 5-bit
D2
5 Clocks
2
D1
3
D0 EQEN
4
5
Figure 13. Simplified Cascaded Serial Data/Clock Timing Diagram
SDIN
SCLKIN
PE1
SCLKOUT
SDOUT
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NB7VPQ16M
D3
1
D2
2
9
D1
3
D0 EQEN
4
5
SDIN
SCLKIN
PE2
SCLKOUT
SDOUT
Publication Order Number:
NB7VPQ16M/D