nb7vpq16m ON Semiconductor, nb7vpq16m Datasheet - Page 10

• Manufacturer Part Number: nb7vpq16m
• Description: 1.8v / 2.5v Cml 12.5 Gbps Programmable Pre-emphasis Copper/cable Driver With Selectable Equalizer Receiver
• Manufacturer: ON Semiconductor

SCLKIN
SCLKOUT
XXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Serial Clock In
Serial Data In
SDIN
XXXXXXXXXXXXXXXXX
SDOUT
Cascaded Applications
The NB7VPQ16M can be cascaded with multiple NB7VPQ16Ms in series for various Equalizer / Pre-Emphasis applications, as
shown in Figure 14.
Serial Data In, SDIN1, is clocked with SCLKIN1 into the cascaded chain of the Pre-Emphasis shift registers, (PE1, PE2 &
PE3), 5-bits per register. Upon the rising edge of the 5
PE1 from SDOUT1 and SCLKOUT1 and enter SDIN2 and SCLKIN2 of PE2….and so on with PE3.
When SLOAD is brought LOW, the PE shift registers of all devices are enabled and data is written into the NB7VPQ16Ms
with the contents of the PE shift registers. When the data transfer is complete, SLOAD is brought HIGH and all NB7VPQ16Ms
are updated simultaneously. After the PE control bits are clocked into their appropriate registers, the Low-to-High transition of
SLOAD will latch the data bits for the Pre-Emphasis DACs.
D3
SCLKIN to SDOUT
1
SLOAD1
SCLKIN to SCLKOUT
XXXXXXXXXX
1
SCLKIN1
D2
SLOAD1
PE3
SDIN1
2
5 Clocks
tpd
2
D1
3
tpd
3
PE1
D0
EQ1
CML
4
Figure 15. Simplified Cascaded Serial Data/Clock Timing Diagram
EQEN D3
4
IN1
Q1
5
Figure 14. Simplified Cascaded Logic Diagram
D3
5
SDOUT1
SCLKOUT1 SCLKIN2
6
D2
6
D2
SLOAD2
PE2
PE3
5 Clocks
7
5 Clocks
SDIN2
D1
SLOAD2
7
D1
8
D0
8
D0 EQEN D3
http://onsemi.com
NB7VPQ16M
9
PE2
EQEN D3
th
EQ2
CML
9
clock of SCLKIN1, the first valid data bit (D3) and 5
10
IN2
Q2
10
10
11
SDOUT2
SCLKOUT2 SCLKIN3
D2
11
D2
PE1
PE2
5 Clocks
12
5 Clocks
SLOAD3
SLOAD3
12
D1
D1
13
SDIN3
13
D0 EQEN D3
D0 EQEN
14
14
PE3
EQ3
15
CML
15
IN3
Q3
16
16
D2
SDOUT3
SCLKOUT3
5 Clocks
PE1
17
D1
18
D0 EQEN
th
19
clock will exit
20