IDT72V2101 IDT [Integrated Device Technology], IDT72V2101 Datasheet

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... Available in the 64-pin Thin Quad Flat Pack (TQFP) High-performance submicron CMOS technology The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input ...

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... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V2101/72V2111 are fabricated using IDT’s high speed submi- cron CMOS technology. PARTIAL RESET (PRS) ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable OE Output Enable ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 Symbol Rating V (2) Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 (Commercial 3.3V ± 0.15V +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time CLKL t Data Setup Time ...

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... When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations reads are performed after a reset, FF will go LOW after D writes to the FIFO 262,144 writes for the IDT72V2101 and 524,288 for the IDT72V2111, respectively. If the FIFO is full, the first read operation will cause HIGH. ...

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... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V2101/ 72V2111 has internal registers for these offsets. Default settings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 IDT72V2101 (262,144 x 9 BIT EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 7FH LOW at Master Reset FFH HIGH at Master Reset 8 7 EMPTY OFFSET (MID-BYTE) REGISTER DEFAULT VALUE 00H LOW at Master Reset ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 WEN REN NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. ...

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... words should have been written into the FIFO and read from the FIFO between Reset (Master or Partial) and the time of Retransmit setup 262,144 for the IDT72V2101 and D = 524,288 for the IDT72V2111 in IDT Standard mode. In FWFT mode 262,145 for the IDT72V2101 and D = 524,289 for the IDT72V2111 ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 When EF goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard mode is selected, every word read including the first word following Retransmit setup requires a LOW on REN to enable the rising edge of RCLK. ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 DATA Data inputs for 9-bit wide data. MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...

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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after after the valid WCLK cycle. D writes to the FIFO (D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. ...

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... In IDT Standard mode reads are performed after reset (MRS), PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (262,144-m) writes for the IDT72V2101 and (524,288-m) writes for the IDT72V2111. The offset “m” is the full offset value ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF If FWFT = HIGH LOW ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing 17 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t RSR t RSR If FWFT = HIGH HIGH ...

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... IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...

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... SKEW2 , then the PAE deassertion may be delayed one extra RCLK cycle. t SKEW2 HIGH LOW PAE offset PAF offset and D = maximum FIFO depth 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. 6. First word latency 2 SKEW1 RCLK ...

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... RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus SKEW2 , then the PAF deassertion may be delayed one extra WCLK cycle. t SKEW2 HIGH PAE Offset PAF offset and D = maximum FIFO depth 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. ( ...

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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...

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... There must be at least two words written to the FIFO before a Retransmit operation can be invoked. WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V2101 and for the IDT72V2111. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes ENS ...

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... PAF offset . maximum FIFO depth. In IDT Standard mode 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. In FWFT mode 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...

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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. 2. For FWFT mode maximum FIFO depth 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...

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... ANDing EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 19 demonstrates a width expansion using two IDT72V2101/ 72V2111 devices from each device form an 18-bit wide output bus ...

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... Figure 20. Block Diagram of 524,288 x 9 and 1,048,576 x 9 Depth Expansion DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V2101 can easily be adapted to applications requiring depths greater than 262,144 and 524,288 for the IDT72V2111 with a 9-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...

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IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 15ns is available as a standard device. 9/14/2000 pgs. 5. 12/18/2000 pgs and 27. 03/27/2001 pgs. 6 and 27. CORPORATE HEADQUARTERS 2975 ...