IDT72V2101 IDT [Integrated Device Technology], IDT72V2101 Datasheet - Page 20

• Manufacturer Part Number: IDT72V2101
• Description: 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. t
2. t
3. LD = HIGH
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
D
Q
WCLK
0
RCLK
0
WEN
REN
t
t
- D
- Q
PAE
PAF
SKEW1
SKEW1
SKEW2
SKEW2
OE
OR
HF
IR
8
8
t
, then the IR assertion may be delayed one extra WCLK cycle.
, then the PAF deassertion may be delayed one extra WCLK cycle.
ENS
t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus t
DS
W
W
1
D
t
OHZ
t
t
DH
ENH
t
WFF
t
ENS
t
OE
W
1
t
A
1
t
SKEW1
W
2
(1)
2
t
A
W
3
t
WFF
t
SKEW2
W
m+2
(2)
Figure 10. Read Timing (First Word Fall Through Mode)
t
A
W
[m+3]
W
[m+4]
t
PAF
W
[
]
t
HF
t
W
A
[
]
W
[D-n-1]
t
A
W
[D-n]
WFF
PAF
1
. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
t
PAE
W
[D-n+1]
W
[D-n+2]
W
[D-1]
t
ENS
t
A
W
D
4669 drw 13
t
REF