IDT72T6480 Integrated Device Technology, IDT72T6480 Datasheet
IDT72T6480
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IDT72T6480 Summary of contents
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... Sequential Flow Control Device DDR SDRAM Control Logic CK WE CAS RAS CK DQS Addr High Density DDR SDRAM x16, x32, x36, or x64 128Mb to 256Mb 1 MRS PRS IOSEL BM[3:0] x48, x24, or x12 REN RCLK/RD RCS JTAG ASYR Control (Boundary Scan) 6358 drw01 OCTOBER 2005 IDT72T6480 DSC-6358/5 ...
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... Table 4 – SFC to DDR SDRAM interface Connections ................................................................................................................................................... 14 Table 5 – Total useable memory based on various configurations ................................................................................................................................... 18 Table 6 – IDT72T6480 Maximum Frequency Based on 166MHz DDR SDRAM ............................................................................................................ 19 Table 7 – IDT72T6480 Maximum Frequency Based on 133MHz DDR SDRAM ............................................................................................................ 19 Table 8 – MIC[2:0] Configurations .................................................................................................................................................................................. 20 Table 9 – Memory Configurations Settings ..................................................................................................................................................................... 21 Table 10 – ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION Figure 1. Sequential Flow-Control Device Block Diagram ................................................................................................................................................ 5 Figure 2a. Configuration 1 - Two Chip Solution .............................................................................................................................................................. 13 Figure 2b. Configuration 2 - Two Chip Solution .............................................................................................................................................................. 13 Figure 2c. Configuration 3 - Three Chip Solution ........................................................................................................................................................... 13 Figure 2d. Configuration 4 - Three Chip Solution ........................................................................................................................................................... 13 Figure 2e. Configuration 5 - Three Chip Solution ........................................................................................................................................................... 13 Figure 2f ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION DESCRIPTION The IDT72T6480 sequential flow-control device is a device incorporating a seamless connection to external DDR SDRAM for significant storage capacity supporting high-speed applications. Both read and write ports of the sequential flow-control can operate independently 133MHz. There is a user selectable correction feature that will correct any erroneous single data bit when reading from the SDRAM ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION Input D[47:0] 48 Register 48 Input Bus-Matching Logic 144 144 QP Cache optional 72 bypass 72 Error Check Bit Detection 72 Generator Correction optional bypass 72 72 Memory Interface Data and Bus-Matching DQ[63:0] Output 48 Q[47:0] Register 48 Output Bus-Matching Logic 144 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN CONFIGURATION A1 BALL PAD CORNER A GND DQ10 DQ8 DQ4 GND B GND GND DQS1 DQ9 DQ5 C DQ14 DQ13 DQ11 DQ12 DQ6 D DQ17 DQ7 DQ16 DQ15 DQS0 E DQ19 DQS2 DQ21 DQ18 DQ20 F DQ23 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN DESCRIPTIONS Symbol Pin No. Name Location READ PORT INTERFACE ASYR (1) V6 Asynchronous Read Port EF/OR V13 Empty Flag/ Output Ready OE U12 Output Enable PAE U13 Programmable Almost Empty Flag Q[47:0] See Pin Data Output Bus No ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN DESCRIPTIONS (Continued) Symbol Pin No. Name Location WRITE PORT INTERFACE (Continued) WCLK/WR V8 Write Clock/ Write Strobe WCS T7 Write Chip Select WEN V7 Write Enable MEMORY INTERFACE A[12:0] See Pin Memory Address No. table Bus ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN DESCRIPTIONS (Continued) Symbol Pin No. Name Location CONTROL AND FEATURE INTERFACE (Continued) (1) JSEL P11 JTAG Select (1) MIC[2:0] MIC2-U10 Memory MIC1-R10 Configuration MIC0-P10 MCLK H1 Master Clock MRS V5 Master Reset (1) MSPEED T8 Memory Speed ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PIN DESCRIPTIONS (Continued) Symbol Pin No. Name Location POWER AND GROUND SIGNALS V See Pin Core V and CC CC No. table Output voltage for DDR SDRAM AV B7, D7 Internal PLL See Pin Output rail voltage DDQ No ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION DETAILED DESCRIPTIONS SEQUENTIAL FLOW-CONTROL STRUCTURE The IDT sequential flow-control (SFC) device is comprised of three inter- faces: input port, output port, and memory interface. The input and output port can operate independently of each other with selectable bus widths of x12, x24, or x48 bits wide ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION EXTERNAL MEMORY CONFIGURATIONS The DDR SDRAM interface of the sequential flow-control (SFC) device has a 64-bit output data bus that provides up to four (16-bit SDRAM) external DDR SDRAM connections. For multiple memory connections, they must be of the same density configuration and speed grade ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION CONNECTING THE DDR SDRAM Below are the various chipset solution configurations available to the sequential flow-control device (see Figure 2a-2g). The external memory interface is designed to seamlessly connect one or more DDR SDRAMs. The output signal names should be connected directly to its corresponding input signal on the DDR SDRAM ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS Data Bus IDT 32 SFC Address Bus 12 CONFIGURATION 1 SFC Outputs DDR SDRAM DQ[31:0] DQ[31:0] DQS[3:0] DQS[3:0] A[11:0] A[11:0] CK, CK CK, CK RAS, CAS RAS, CAS BA[1:0] BA[1: DDR SDRAM Hard wired pins CKE → ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS(Continued Data Bus 256Mb IDT 16 32 DDR SFC SDRAM Address Bus 13 6358 drw08 Data Bus 256Mb IDT 36 16 DDR SFC SDRAM Address Bus ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS(Continued) CONFIGURATION 7 SFC Outputs DDR SDRAM #1 DQ[15:0] DQ[31:16] DQ[47:32] DQ[63:48] DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 A[12:0] CK, CK RAS, CAS BA[1:0] WE DDR SDRAM Hard wired pins CKE → → ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION Sequential Flow-Control Device Sequential Flow-Control Device DQS[3:0] DQS[3: CAS CAS RAS RAS DQ[31:0] DQ[31:0] 32 A[11:0] A[11:0] 12 Figure 3. Memory Interface Connection (Single Chip DQS[7:0] DQS[3: CAS CAS RAS ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION TOTAL AVAILABLE MEMORY USAGE The sequential flow-control (SFC) is designed to efficiently use as much of the DDR SDRAM memory as possible, but due to the discontinuity between the SFC bus width (x48) and the DDR SDRAM interface (x16 or x32), some columns in a row of the SDRAM will not be used ...
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... Configuration 3 100MHz 133MHz Configuration 4 66MHz 66MHz Configuration 5 50MHz 66MHz Configuration 6 66MHz 66MHz Configuration 7 100MHz 133MHz TABLE 7 – IDT72T6480 MAXIMUM FREQUENCY BASED ON 133MHz DDR SDRAM Bus-Width x48 EDC On EDC Off Configuration 1 33MHz 50MHz Configuration 2 25MHz 25MHz Configuration 3 66MHz 100MHz Configuration 4 50MHz ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION ERROR DETECTION AND CORRECTION The Error Detection and Correction (EDC) feature is available to ensure data integrity between the DDR SDRAM interface and the SFC. The EDC corrects all single bit hard and soft errors that are accessed from the DDR SDRAM. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION SETTING THE MEMORY INTERFACE SIGNALS The configurations listed in Figure 2a-2g can be programmed into the sequential flow-control device by using the MIC[2:0], MTYPE[1:0], and TABLE 9 – MEMORY CONFIGURATIONS SETTINGS MIC[2:0] Configuration 1 000 - EDC Off ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION TABLE 10 – DEVICE CONFIGURATION Signal Pins Static State Configuration ASYR 0 Read port configured in asynchronous mode 1 Read port configured in synchronous mode ASYW 0 Write port configured in asynchronous mode 1 Write port configured in synchronous mode BM[3:0] — ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION SIGNAL DESCRIPTIONS INPUTS DATA INPUTS ( Data inputs for 48-bit wide data ( data inputs for 24-bit wide data data inputs for 12-bit wide data ( CONTROLS MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is toggled LOW then HIGH ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + t after the valid RCLK cycle. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION MEMORY CONFIGURATION (MIC[2:0]) These signals enable the EDC feature of the device. See Table 8, MIC[2:0] Configurations for more information. MEMORY SPEED (MSPEED) This pin is used to determine the memory interface clock speed (CK and CK) for the external memory used ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the SFC is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the SFC is not empty. Figure 10, Empty Boundary – ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG T Maximum Junction Temp. JMAX I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION DC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.125V 0°C to +70°C;Industrial I/O Type Symbol SFC Input I Input leakage current LI (LVTTL) V Input High Voltage IH V Input Low Voltage IL SFC Output I Output leakage current ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION 2.5V LVTTL AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 2.5V SSTL AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 3 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION AC ELECTRICAL CHARACTERISTICS = 2.5V ± 5%, T (Commercial 0°C to +70°C;Industrial Symbol Parameter f Synchronous Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION AC ELECTRICAL CHARACTERISTICS ASYNCHRONOUS TIMING = 2.5V ± 5%, T (Commercial 0°C to +70°C;Industrial Symbol Parameter f Asynchronous Clock Cycle Frequency A t Data Access Time Aa t Cycle Time CYC t Cycle High Time ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION MRS REN WEN SREN SWEN EF If IDT mode is selected OR If FWFT mode is selected FF If IDT mode is selected IR If FWFT mode is selected CK The clock may not be locked to the required operating frequency before ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION PRS REN WEN SREN SWEN If IDT mode is selected FWFT mode is selected FF If IDT mode is selected IR If FWFT mode is selected Q[47:0] PAF PAE Symbol Parameter Min. t Reset Pulse Width Reset Setup Time ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION WCLK t ENS WEN t ENS D[47:0] Word 0 RCLK REN EF Q[47:0] NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle 1. t SKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION RCLK t t ENS ENH REN t REF Q[47: (1) t SKEW1 WCLK t ENS WEN t DS Word 0 D[47:0] NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle (plus t 1 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION WCLK t ENS WEN D[47:0] D-1 FF RCLK REN Q[47:0] Previous Word in Register NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle 1 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION RCLK REN t A Word 1 Word 2 Q[47:0] OE NOTE: 1. Settings: RCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. RCLK REN t A Word 1 Word 2 Q[47:0] RCS NOTE: 1. Settings LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION WCLK t ENS WEN t DS D[47:0] Word 0 RCLK REN EF Previous Word in Register D[47:24] Q[23:0] NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK 1. t SKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION WCLK t ENS WEN t DS D[23:0] Word 0 Q[23:0] RCLK REN EF Q[47:0] NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle 1. t SKEW1 is not met, then EF de-assertion may be delayed one extra RCLK cycle. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION WCLK t ENH WEN D[47:0] Word PAE n words or less in Memory words or less in Memory t SKEW2 RCLK 1 REN Q[47:0] NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK 1 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION RD Q[47:0] Word PAF NOTES PAF offset, see Table 10 for information on PAF offset values density of SFC. 2. Settings LOW, RCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 3. Asynchronous read is available in IDT standard mode only. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION WR D[47:0] RD Q[47:0] EF NOTES: 1. Settings LOW, RCS = LOW, WCS = LOW, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 2. Asynchronous read is available in IDT standard mode only. Figure 26. Asynchronous Empty Boundary - IDT Standard Mode WR D[47:0] RD Q[47:0] FF NOTES: 1 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION SCLK t SENS SWEN BIT 0 NOTES: 1. Settings: JSEL = LOW the required number of bits to program the PAE and PAF offset registers. See Table 12 for the numbers based on the values external configurations. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION t 1 TCK t 3 TDI/ TMS t TDO SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions (1) Data Output t DO (1) Data Output Hold t DOH Data Input rise=3ns fall=3ns NOTE: 1. 50pf loading on external output signals. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION JTAG TIMING SPECIFICATIONS (IEEE 1149.1 COMPLIANT) The JTAG test port in this device is fully compliant with the IEEE Standard Test Access Port (IEEE 1149.1) specifications. Four additional pins (TDI, TDO, TMS and TCK) are provided to support the JTAG boundary scan interface. ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION 1 Input is 0 TMS NOTES: 1. Five consecutive 1's at TMS will reset the TAP. 2. TAP controller resets automatically upon power-up. Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram All state transitions within the TAP controller occur at the rising edge of the TCLK pulse ...
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... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72T6480, the Part Number field contains the following values: Device Part# Field IDT72T6480 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION CLAMP The optional CLAMP instruction sets the outputs of an device to logic levels determined by the contents of the boundary-scan register and selects the one- bit bypass register to be connected between TDI and TDO. Before loading this instruction, the contents of the boundary-scan register can be preset with the SAMPLE/PRELOAD instruction ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION DEPTH EXPANSION CONFIGURATION The sequential flow-control (SFC) device can be connected with multiple SFCs in depth expansion to provide additional storage density that’s greater than 1Gb. In depth expansion mode, two or mode devices are connected through a common transfer interface, as shown in Figure 34 ...
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... IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION WIDTH EXPANSION CONFIGURATION The sequential flow-control (SFC) device can be connected with another SFCs in width expansion to support bus-widths greater than 36-bits. This configuration connects the input and output bus of two devices together to create a wider bus ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed DATASHEET DOCUMENT HISTORY 07/29/2004 pgs 7-11, 13-25, 27-29, 31-43, 47, 49, and 51. 04/11/2005 pg. 10. 04/15/2005 pg. 10 and 51. 06/28/2005 pgs. 16 and 24. 10/10/2005 pgs. ...