IDT72T6480 Integrated Device Technology, IDT72T6480 Datasheet - Page 7

• Manufacturer Part Number: IDT72T6480
• Description: X48 Sequential Flow-control Device Up To 1gigabit
• Manufacturer: Integrated Device Technology

PIN DESCRIPTIONS
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
READ PORT INTERFACE
ASYR
EF/OR
OE
PAE
Q[47:0]
RCLK/
RD
RCS
REN
SREN
WRITE PORT INTERFACE
ASYW
D[47:0]
FF/IR
PAF
SWEN
Symbol
(1)
(1)
Location
No. table
No. table
See Pin
See Pin
Pin No.
V13
U12
U13
V12
V10
V11
R12
T12
T11
V6
V9
T6
Asynchronous
Read Port
Empty Flag/
Output Ready
Output Enable
Programmable
Almost Empty Flag
Data Output Bus
Read Strobe
Read Chip Select
Read Enable
Serial Read Enable
Asynchronous
Write Port
Data Inputs
Full Flag/
Input Ready
Programmable
Almost Full Flag
Serial Write Enable
Read Clock/
Name
2.5V LVTTL device must operate in IDT Standard mode and the read enable must be tied to GND.
2.5V LVTTL there is valid data available at the outputs.
2.5V LVTTL pin is LOW.
2.5V LVTTL in the sequential flow-control device is less than offset n, which is stored in the empty offset
2.5V LVTTL
2.5V LVTTL If asynchronous operation of the read port is selected, a rising edge on RD reads data
2.5V LVTTL
2.5V LVTTL
2.5V LVTTL each rising edge of SCLK, one bit of data is shifted out of this serial shift register through the
2.5V LVTTL device must operate in IDT Standard mode and the write enable must be tied to GND.
2.5V LVTTL
2.5V LVTTL is space available for writing to the device memory.
2.5V LVTTL in the sequential flow-control device is more than offset m, which is stored in the full offset
2.5V LVTTL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
3.3V
A HIGH on this input during master reset will select synchronous read operation for the
output port. A LOW will select asynchronous operation. If asynchronous is selected the
In IDT Standard mode, the EF function is selected. EF indicates whether or not the device
memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not
Asynchronous three-state control of the data outputs. All data outputs Q[47:0] will be placed
in high-impedance if this pin is HIGH. Conversely, all data outputs will be active when this
This is the programmable almost empty flag that can be used as an early indicator for the
empty boundary condition of the internal memory. PAE goes LOW if the number of words
register. PAE goes HIGH if the number of words in the sequential flow-control device is
greater than or equal to the offset n.
Data outputs for a 48, 24, and 12-bit bus.
This is a dual function pin. If synchronous operation of the read port is selected, the rising
edge of RCLK reads data from the sequential flow-control device when REN is enabled.
from the sequential flow-control device without the need of a free-running input read clock.
Synchronous three-state control of the data outputs. Provides another means of controlling
the data outputs synchronous to RCLK. Can be regarded as a second output enable signal.
REN enables RCLK for reading data from the sequential flow-control device. If
asynchronous mode is selected on the read port, this signal should be tied to GND.
When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and
PAF offset registers are copied to a serial shift register. While SREN is maintained LOW, on
SO output pin used only when JSEL = 0.
A HIGH on this input during master reset will select synchronous write operation for the
input port. A LOW will select asynchronous operation. If asynchronous is selected the
Data inputs for a 48, 24, and 12-bit bus.
In IDT Standard mode, the FF function is selected. FF indicates whether or not the device
memory is full. In FWFT mode, the IR function is selected. IR indicates whether or not there
This is the programmable almost full flag that can be used as an early indicator for the full
boundary condition of the internal memory. PAF goes HIGH if the number of free locations
register. PAF goes LOW if the number of free locations in the sequential flow-control device
is less than or equal to the offset m.
On each rising edge of SCLK when SWEN is LOW, data from the SI pin is serially loaded
into the PAE and PAF registers used only when JSEL = 0.
7
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 10, 2005