IDT72T6480 Integrated Device Technology, IDT72T6480 Datasheet - Page 18

• Manufacturer Part Number: IDT72T6480
• Description: X48 Sequential Flow-control Device Up To 1gigabit
• Manufacturer: Integrated Device Technology

TOTAL AVAILABLE MEMORY USAGE
the DDR SDRAM memory as possible, but due to the discontinuity between the
SFC bus width (x48) and the DDR SDRAM interface (x16 or x32), some
columns in a row of the SDRAM will not be used. As a result, the total usable
memory will be slightly less than the total available memory in the SDRAM. Table
5 outlines the total usable memory for the various configurations depending on
TABLE 5 – TOTAL USEABLE MEMORY BASED ON VARIOUS CONFIGURATIONS
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
The sequential flow-control (SFC) is designed to efficiently use as much of
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
1 x [16Mb x 16]
3 x [16Mb x 16]
4 x [16Mb x 16]
1 x [4Mb x 32]
1 x [8Mb x 32]
2 x [4Mb x 32]
2 x [8Mb x 32]
2 x [4Mb x 32]
2 x [8Mb x 32]
2 x [8Mb x 16]
3 x [8Mb x 16]
Total DDR SDRAM
Density
128Mb
256Mb
256Mb
256Mb
512Mb
256Mb
512Mb
256Mb
384Mb
768Mb
1Gb
Memory (EDC off)
18
Total Usable
whether or not the Error Detection and Correction (EDC) feature is selected.
If the EDC feature is selected, 8 syndrome bits will be generated per every 64
bits of data. Therefore every third write burst to the SDRAM will send out the
8 syndrome bits, resulting in 24 unused bits in the column. Therefore, using the
EDC feature, there will be significantly less usable memory of data storage. The
EDC function is described in the Error Detection and Correction section of this
datasheet.
1008Mb
108Mb
252Mb
216Mb
216Mb
504Mb
122Mb
284Mb
252Mb
284Mb
567Mb
Memory (EDC on)
Total Usable
144Mb
144Mb
144Mb
288Mb
108Mb
252Mb
144Mb
252Mb
504Mb
576Mb
72Mb
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 10, 2005