IDT7130 Integrated Device Technology, IDT7130 Datasheet - Page 13

• Manufacturer Part Number: IDT7130
• Description: HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
• Manufacturer: Integrated Device Technology

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
FUNCTIONAL DESCRIPTION
The IDT7130/IDT7140 provides two ports with separate con-
trol, address and I/O pins that permit independent access for
reads or writes to any location in memory. The IDT7130/
IDT7140 has an automatic power down feature controlled by
CE
the respective port to go into a standby mode when not
selected (
entire memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (
right port writes to memory location 3FE (HEX), where a write
is defined as the
port clears the interrupt by access address location 3FE
access when
the right port interrupt flag (
writes to memory location 3FF (HEX) and to clear the interrupt
flag (
3FF. The message (8 bits) at 3FE or 3FF is user-defined,
since it is an addressable SRAM location. If the interrupt
function is not used, address locations 3FE and 3FF are not
used as mail boxes, but as part of the random access
memory. Refer to Table II for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The Busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the
write inhibit input pin. Normal operation can be programmed
by tying the
operations can be prevented to a port by tying the Busy pin for
that port Low.
. The
INT
CE
R
CE
), the right port must access the memory location
controls on-chip power down circuitry that permits
CE
BUSY
= V
R
CE
IH
=
). When a port is enabled, access to the
OE
= R/
pins High. If desired, unintended write
R =
W
V
INT
= V
IL,
R/
R
BUSY
IL
) is asserted when the left port
W
per the Truth Table. The left
INT
is a "don't care". Likewise,
pin operates solely as a
L
) is asserted when the
6.01
The Busy outputs on the IDT7130 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy
pin is an output if the part is Master (IDT7130), and the Busy
pin is an input if the part is a Slave (IDT7140) as shown in
Figure 4.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
270
BUSY
5 V
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7130 (Master) and IDT7140 (Slave) RAMs.
L
MASTER
Dual Port
RAM
BUSY
MASTER
Dual Port
RAM
BUSY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(L)
(L)
W
BUSY
BUSY
signal or the byte enables. Failure to
CE
CE
(R)
(R)
SLAVE
Dual Port
RAM
BUSY
SLAVE
Dual Port
RAM
BUSY
(L)
(L)
BUSY
BUSY
CE
CE
(R)
(R)
2689 drw 18
BUSY
5 V
R
13
270