ics1574b Integrated Device Technology, ics1574b Datasheet
ics1574b
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ics1574b Summary of contents
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... User Programmable Laser Engine Pixel Clock Generator Pixel Clock Generator Description The ICS1574B is a very high performance monolithic phase- locked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed- mode technology, the ICS1574B provides a low cost solution for high-end pixel clock generation for a variety of laser en- gine product applications ...
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... TSD ICS1574B ...
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... ICS1574B User Programmable Laser Engine Pixel Clock Generator PCLK Programmable Divider The ICS1574B has a programmable divider (referred to in Fig- ure 1 as the PCLK divider) that is used to generate the PCLK clock frequency for the pixel clock output. The modulus of this divider may be set 10, 12 under register control ...
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... User Programmable Laser Engine Pixel Clock Generator PLL Post-Scaler A programmable post-scaler may be inserted between the VCO and the PCLK divider of the ICS1574B. This is useful in generating lower frequencies, as the VCO has been optimized for high-frequency operation. The post-scaler is not affected by the PCLKEN input. ...
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... It is also desirable to ground the crystal can to the ground plane, if possible external reference frequency source used with the ICS1574B important that it be jitter-free. The ris- ing and falling edges of that signal should be fast and free of noise for best results. ...
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... BOTH of these pins should connect to the ground plane of the PCB as close to the package as is possible. The ICS1574B has a VDDO pin which is the supply of +5 volt power to the output driver. This pin should be con- nected to the power plane (or bus) using standard high-frequency decoupling practice. That is, capacitors IDT™ ...
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... User Programmable Laser Engine Pixel Clock Generator Register Mapping — ICS1574B NOTE not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to automatically generate all register values based on requirements. Contact factory for details. BIT(S) BIT REF. ...
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... Otherwise, modulus = 7 for "value" underflows of the prescaler, and modulus = 6 thereafter until M counter underflows TSD µ ICS1574B ...
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... Must be set to 0. Disables the PCLK divider when set to 1 regardless of PCLKEN input state. Must be set to 0. Reference divider modulus control bits. Modulus = value +1. PLL locks to rising edge of XTAL1 input when REFPOL = 1, falling edge of XTAL1 when REFPOL = ICS1574B TSD ICS1574B ...
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... ICS1574B ...
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... – — — TSD µ A µ ICS1574B ...
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... Ordering Information ICS1574BM / ICS1574BEB Example: ICS 1574B M LF IDT™ / ICS™ User Programmable Laser Engine Pixel Clock Generator ...
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... ICS1890 ICS1574B MK1491-14 ICS280 OPTi ACPI Firestar Clock Source User Programmable Laser Engine Pixel Clock Generator Auto-Negotiation Advertisement Register (register 4 [0x04]) TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales ...