ics1574b Integrated Device Technology, ics1574b Datasheet - Page 8

• Manufacturer Part Number: ics1574b
• Description: User Programmable Laser Engine Pixel Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ User Programmable Laser Engine Pixel Clock Generator
ICS1574B
User Programmable Laser Engine Pixel Clock Generator
ICS1574B
BIT(S)
15
16
17 – 24
25 – 27
28
29 – 30
31
32
33 – 38
39
40
41 – 44
BIT REF.
Reserved
AUX_PCLK
When in the AUX-EN test mode, this bit controls the
Reserved
V[0]..V[2]
Reserved
P[0]..P[1]
Reserved
P[2]
See text.
M[0]..M[5]
PCLKEN_POL
DBLFREQ
12 /14).
A[0]..A[3]
Must be set to 0 except when in the AUX-EN test mode.
Sets the gain of the phase detector according to this table:
M counter control bits. Modulus = value + 1.
When = 0, PCLK output enabled when PCLKEN input is
DESCRIPTION
Must be set to 0.
PCLK output.
Must be set to 0.
Sets the gain of VCO
Must be set to 1.
Must be set to 0.
Phase detector tuning bit. Should normally be set to one.
low. When = 1, PCLK output enabled when PCLKEN input
is high.
Doubles modulus of dual-modulus prescaler (from 6 / 7 to
Controls A counter. When set to zero, modulus = 7.
Otherwise, modulus = 7 for "value" underflows of the
prescaler, and modulus = 6 thereafter until M counter
underflows.
8
8
V
[ P
[
0
0
1
1
1
1
1
1
] 1
] 2
V
[ P
[
0
0
0
0
1
1
1
1
] 0
] 1
G
A
V
I
[
0
0
1
1
N
] 0
. 0
. 0
0
1
µ (
5 .
5 .
5 0
5 1
A
r /
d a
a i
V
) n
(
M
C
O
H
0 3
5 4
0 6
0 8
z
G
V /
A
o
) t l
I
N
ICS1574B
TSD