ics1574b Integrated Device Technology, ics1574b Datasheet - Page 5

• Manufacturer Part Number: ics1574b
• Description: User Programmable Laser Engine Pixel Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ User Programmable Laser Engine Pixel Clock Generator
ICS1574B
User Programmable Laser Engine Pixel Clock Generator
Reference Oscillator
and Crystal Selection
The ICS1574B has circuitry on-board to implement a
Pierce oscillator with the addition of only one external
component, a quartz crystal. Pierce oscillators operate the
crystal
anti- (also called parallel-) resonant mode. See the AC
Characteristics for the effective capacitive loading to
specify when ordering crystals.
Series-resonant crystals may also be used with the
ICS1574B. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the
can (typically 0.025 – 0.05%).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend
that the crystal be mounted as closely as possible to the
package. Avoid routing digital signals or the ICS1574B
outputs underneath or near these traces. It is also desirable
to ground the crystal can to the ground plane, if possible.
If an external reference frequency source is to be used with
the ICS1574B, it is important that it be jitter-free. The ris-
ing and falling edges of that signal should be fast and free
of noise for best results.
The loop phase can be locked to either the rising or falling
edges of the XTAL1 input signals, and is controlled by
Bit 56.
Power-On Initialization
The ICS1574B has an internal power-on reset circuit that
performs the following functions:
These functions should allow initialization for most appli-
cations that cannot immediately provide for register
programming upon system power-up.
Because the power-on reset circuit is on the VDD supply,
and because that supply is filtered, care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD sup-
ply reaches 4 volts.
1) Selects the modulus of the PCLK divider to
2) Sets the multiplexer to pass the reference
be four (4).
frequency to PCLK divider input.
in
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5
Programming Notes
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Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1574B supports
this through a register programmable mode, AUX-EN.
When this mode is set, a register bit directly controls the
logic level of the PCLK pin. This mode is activated when
the S[0] and S[1] bits are both set to logic 1. See Register
Mapping for details.
VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
Divider Range: For best results in normal situations
keep the reference divider modulus as short as possible
(for a frequency at the output of the reference divider in
the few hundred kHz to several MHz range). If you
need to go to a lower phase comparator reference fre-
quency (usually required for increased frequency
accuracy), that is acceptable, but jitter performance will
suffer somewhat.
VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as
shown here:
Phase Detector Gain: For most applications and divider
ranges, set P [1, 0] = 10 and set P[2] = 1. Under some
circumstances, setting the P [2] bit “on” can reduce
jitter. During operation at exact multiples of the crystal
frequency, P[2] bit = 0 may provide the best jitter per-
formance.
V
C
O
4
5
6
7
G
A
I
N
M
A
X
1
2
3
4
F
ICS1574B
0 0
0 0
0 0
0 0
R
E
M
M
M
M
Q
H
H
U
H
H
z
z
E
z
z
N
C
Y
ICS1574B
TSD