gtlp18t612 Fairchild Semiconductor, gtlp18t612 Datasheet
gtlp18t612
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gtlp18t612 Summary of contents
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... GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver General Description The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’ ...
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... A-to-B Open Drain Outputs Functional Description The GTLP18T612 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively ...
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Truth Table (Note 1) CEAB OEAB Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 5) 0. Output Sink Current into A Port Output ...
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DC Electrical Characteristics Symbol Ports V 3.45V CCQ GND Port and V 3.45V (Note 10) Control Pins A ...
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AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature for B Port and for A Port From Symbol (Input PLH t PHL t LEAB PLH ...
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Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Open PLH PHL PLZ PZL t /t GND PHZ PZH Note A: C includes probes and Jig capacitance. L Voltage Waveform - Propagation ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 8 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...