ICL7104-16CPL Intersil, ICL7104-16CPL Datasheet - Page 8

• Manufacturer Part Number: ICL7104-16CPL
• Description: 16 BIT A/D CONVERTER
• Manufacturer: Intersil

Specifications of ICL7104-16CPL

• Rohs Status: RoHS non-compliant
• Other names: NT5019

Detailed Description
ANALOG SECTION
Figure 6 shows the equivalent Circuit of the Analog Section
of both the ICL7104/8052 and the ICL7104/8068 in the 3
different phases of operation. If the Run/Hold pin is left open
or tied to V+, the system will perform conversions at a rate
determined by the clock frequency: 131,072 for - 16 and
32,368 for - 14 clock periods per cycle (see Figure 8
conversion timing).
Auto-Zero Phase I (Figure 6A)
During Auto-Zero, the input of the buffer is shorted to analog
ground thru switch 2, and switch 1 closes a loop around the
integrator and comparator. The purpose of the loop is to
charge the Auto-Zero capacitor until the integrator output no
longer changes with time. Also, switches 4 and 9 recharge
the reference capacitor to V
Input Integrate Phase II (Figure 6B)
During input integrate the Auto-Zero loop is opened and the
analog input is connected to the buffer input thru switch 3.
(The reference capacitor is still being charged to V
during this time.) If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous sate (Auto-Zero). Thus the integrator
output will not change but will remain stationary during the
entire Input Integrate cycle. If V
INTERNAL
LATCH PULSE IF
(EXTERNAL
MODE PIN
MODE
O/R, POL
SIGNAL)
CLOCK 1 H
EITHER:
BITS 1-5
(PIN 25)
MODE “HI”
INTERNAL
CE/LD
HBEN
OR
LBEN
01-14
SEN
NORM
UART
HANDSHAKE MODE
H
H
H
H
H
H
L
L
L
L
L
L
L
DON’T CARE
TRIGGERED BY
t
CWH
REF
t
t
ME
MB
t
CEL
t
.
MW
IN
is not equal to zero, an
OR
FIGURE 5. HANDSHAKE MODE TIMING DIAGRAM
EXT
IGNORED
DATA VALID, STABLE
t
SM
t
CDH
t
CBL
t
CEH
-16 HAS EXTRA (MBEN) PHASE
EXT
ICL7104
REF
8
unbalanced condition exists compared to the Auto-Zero
phase, and the integrator will generate a ramp whose slope
is proportional to V
the ramp is latched into the polarity F/F.
Deintegrate Phase III (Figures 6C and 6D)
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switches 6 and 9 or 7 and 8. If the input signal was positive,
switches 7 and 8 are closed and a voltage which is V
more negative than during Auto-Zero is impressed on the
buffer input. Negative inputs will cause +V
to the buffer input via switches 6 and 9. Thus, the reference
capacitor generates the equivalent of a (+) reference or a (-)
reference from the single reference voltage with negligible
error. The reference voltage returns the output of the inte-
grator to the zero-crossing point established in Phase I. The
time, or number of counts, required to do this is proportional
to the input voltage. Since the Deintegrate phase can be
twice as long as the Input integrate phase, the input voltage
required to give a full scale reading = 2V
NOTE: Once a zero crossing is detected, the system automatically
reverts to Auto-Zero phase for the leftover Deintegrate time (unless
RUN/HOLD is manipulated, see RUN/HOLD input in detailed
description, digital section).
THREE-STATE
DON’T CARE
t
SS
t
CDL
DATA VALID, STABLE
IGNORED
t
CBH
IN
. At the end of this phase, the sign of
THREE-STATE WITH PULLUP
t
t
CBZ
CEZ
REF
REF
.
to be applied
DON’T CARE
STABLE
REF