ICL7104-16CPL Intersil, ICL7104-16CPL Datasheet - Page 13

• Manufacturer Part Number: ICL7104-16CPL
• Description: 16 BIT A/D CONVERTER
• Manufacturer: Intersil

Specifications of ICL7104-16CPL

• Rohs Status: RoHS non-compliant
• Other names: NT5019

Run/Hold Input
When the Run/Hold input is connected to V+ or left open
(this input has pullup resistor to ensure a high level when the
pin is left open), the circuit will continuously perform
conversion cycles, updating the output latches at the end of
every Deintegrate (Phase III) portion of the conversion cycle
(See Figure 8). (See under “Handshake Mode” for
exception.) In this mode of operation, the conversion cycle
will be performed in 131,072 for 7104-16 and 32768 for
7104-14 clock periods, regardless of the resulting value.
If Run/Hold goes low at any time during Deintegrate (Phase
III) after the zero crossing has occurred, the circuit will
immediately terminate Deintegrate and jump to Auto-Zero.
This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If Run/Hold stays or
goes low, the converter will ensure a minimum Auto-Zero
time, and then wait in Auto-Zero until the Run/Hold input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STATUS output will
go high) seven clock periods after the high level is detected
RUN/HOLD
INTEGRATOR
INTERNAL
INTERNAL
OUTPUT
STATUS
CLOCK
LATCH
INPUT
OUTPUT
SECTION
ANALOG
TO
COMP OUT
AZ
INT
DEINT(+)
DEINT(-)
INITIAL
CLEAR
STATUS
AT ZERO CROSSING
DEINT TERMINATED
CONVERSION
CONTROL
2
LOGIC
FIGURE 10. RUN/HOLD OPERATION
DETECTION
FIGURE 9. DIGITAL SECTION
R/H
26
ICL7104
CLOCK
18/16 THREE-STATE OUTPUTS
(1)
13
24
OSCILLATOR
AND CLOCK
CIRCUITRY
OPTION
at Run/Hold. See Figure 10 for details.
Using the Run/Hold input in this manner allows an easy
“convert on demand” interface to be used. The converter
may be held at idle in Auto-Zero with Run/Hold low. When
Run/Hold goes high the conversion is started, and when the
STATUS output goes low the new data is valid (or trans-
ferred) to the UART - see Handshake Mode). Run/Hold may
now go low terminating Deintegrate and ensuring a minimum
Auto-Zero time before stopping to wait for the next
conversion. Alternately, Run/Hold can be used to minimize
conversion time by ensuring that it goes low during Deinte-
grate, after zero crossing, and goes high after the hold point
is reached. The required activity on the Run/Hold input can
be provided by connecting it to the CLOCK3 (-14), CLOCK2
(-16) Output. In this mode the conversion time is dependent
on the input value measured. Also refer to Intersil Applica-
tion Bulletin A030 for a discussion of the effects this will have
on Auto-Zero performance.
If the Run/Hold input goes low and stays low during Auto-
Zero (Phase I), the converter will simply stop at the end of
CLOCK
MAX
MIN
18/16 LATCHES
18/16 BIT COUNTER
(2)
23
CLOCK
7161
8185
-14
LATCH
CLOCK
(3)
25
28665
32761
-16
MODE
HANDSHAKE
HOLD STATE
STATIC IN
21
LOGIC
SEND
27
7 COUNTS
HBEN
(-16 ONLY)
CE/LD
MBEN
LBEN
INT
PHASE