ICL7104-16CPL Intersil, ICL7104-16CPL Datasheet

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... Copyright © Intersil Americas Inc. 2002. All Rights Reserved 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter Description The ICL7104, combined with the ICL8052 or ICL8068, forms a member of Intersil’ high performance A/D converter family. The ICL7104-16, performs the analog switching and digital function for a 16-bit binary A/D converter, with full three-state output, UART handshake capability, and other outputs for easy interfacing ...

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... ANALOG SW7 INPUT SW9 35 ANALOG GND 38 34 REF CAP (1) REF CAP (2) C REF FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM Pin Descriptions PIN NO. SYMBOL OPTION 1 V++ Positive Supply Voltage: Nominally +15V. 2 GND Digital Ground: 0V, ground return. 3 STTS Status Output: HI during integrate and deintegrate until data is latched. LO when analog section is in auto-zero configuration ...

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... Reference Capacitor: Negative Side. 35 AN. GND Analog Ground: Input low side and reference low side. 36 A-Z Auto-Zero node Voltage Reference: Input (positive side). REF 38 REFCAP1 Reference Capacitor: Positive side. 39 COMP-IN Comparator Input: From 8052/8068 Negative Supply Voltage: Nominally -15V. ICL7104 DESCRIPTION (-16 (-14) clock ...

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... Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are applied. ...

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... Apply only when these pins are inputs, i.e., the mode pin is low, and the 7104 is not in handshake mode. 8. Apply only when these pins are outputs, i.e., the mode pin is high, or the 7104 is in handshake mode. 9. Clock circuit shown in Figures 14 and 15. 10. V+ must not be more positive than V++. System Electrical Specifications: ICL8068/ICL7104 PARAMETER Zero Input Reading Ratiometric Error (Note 13) Linearity Over ± ...

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... System Electrical Specifications: ICL8052/ICL7104 PARAMETER Leakage Current at Input (Note 14) Zero Reading Drift Scale Factor Temperature Coefficient NOTES: 11. Tested with low dielectric absorption integrating capacitor. 12. The input bias currents are junction leakage currents which approximately double for every Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation ...

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... Clock 1 High to Data Enabled Delay. CDH t Clock 1 Low to Data Disabled Delay. CDL t Send ENABLE Set-Up Time Clock 1 High to XBEN Disabled Delay. CBZ t Clock 1 High to CE/LD Disabled Delay. CEZ t Clock 1 High Time. CWH ICL7104 t DHB DATA VALID FIGURE 4. DIRECT MODE TIMING DIAGRAM MIN - - - - - - - MIN - - ...

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... Detailed Description ANALOG SECTION Figure 6 shows the equivalent Circuit of the Analog Section of both the ICL7104/8052 and the ICL7104/8068 in the 3 different phases of operation. If the Run/Hold pin is left open or tied to V+, the system will perform conversions at a rate determined by the clock frequency: 131,072 for - 16 and 32,368 for - 14 clock periods per cycle (see Figure 8 conversion timing) ...

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... I/P BUFFER INTEGRATOR - REF 4 C REF FIGURE 6B. PHASE II INTEGRATE INPUT R INT +AN I/P BUFFER - REF 4 C REF FIGURE 6C. PHASE III + DEINTEGRATE ICL7104 C INT COMP ZERO A2 CROSS. A3 DET POL FIGURE 6A. PHASE I AUTO-ZERO C INT COMP ZERO A2 CROSS. A3 DET POL C INT INTEGRATOR COMP ZERO A2 CROSS DET ...

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... The circuit recommended for doing this with the ICL8068/ICL7104 is shown in Figure 7. With care- ful layout, the circuit shown can achieve effective input noise voltages on the order 2µV, allowing full 16-bit use with full scale inputs of a low as 150mV ...

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... REF 8068 -1.2V 5 +BUF IN 13 +INT ICL7104 FIGURE 7. ADDING BUFFER GAIN TO ICL8068 COUNTS PHASE I PHASE II 32768 32768 8192 8192 POLARITY DETECTED INT PHASE II IN FIGURE 8. CONVERSION TIMING to give 9 volt swing for full scale inputs. This is a compromise between possibly saturating the integrator (at +14 volts) due ...

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... REF The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. The resolution of the ICL7104 at 16 bits is one part in 65536, or 15.26ppm. Thus, if the reference has a temperature coefficient of 50ppm/C (on board reference) a temperature change of 1/3C will introduce a one-bit absolute error. For this reason rec- ...

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... Auto-Zero until the Run/Hold input goes high. The converter will begin the Integrate (Phase II) portion of the next conversion (and the STATUS output will go high) seven clock periods after the high level is detected ICL7104 18/16 THREE-STATE OUTPUTS 18/16 LATCHES 18/16 BIT COUNTER ...

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... This timing diagram shows the relationships that occur using an industry-standard IM6402/3 CMOS UART to interface to serial data channels. In this interface, the SEN input to the ICL7104 is driven by the TBRE (Transmitter Buffer Register Empty) output of the UART, and the CE/LD terminal of the ICL7104 drives the TBRL (Transmitter Buffer Register Load) input to the UART ...

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... When the UART has transferred the data to the Transmitter Register and cleared the Transmitter Buffer Register, the TBRE returns high. On the next ICL7104 internal clock high to low edge, the high order byte outputs are disabled, and one-half internal clock later, the HBEN output returns high. ...

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... INTERNAL NORM MODE SEN INPUT (UART TBRE) CE/LOAD (UART TBRL) HBEN HIGH BYTE DATA MBEN MIDDLE BYTE DATA LBEN LOW BYTE DATA DON’T CARE FIGURE 12. HANDSHAKE - TYPICAL UART INTERFACE TIMING ICL7104 DATA VALID DATA VALID THREE-STATE HIGH IMPEDANCE 16 DATA VALID ...

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... CLOCK NOTE: Clock 3 has the same output drive as the bit outputs. FIGURE 14. RC OSCILLATOR (ICL7104-14 ONLY result of pin count limitations, the ICL7104-16 has only CLOCK 1 and CLOCK 2 available, and cannot be used oscillator. The internal clock will correspond to the inverse of the signal on CLOCK 2. Figure 15 shows a crystal oscillator circuit, which can be used with both 7104 versions ...

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... Schottky rectifier diode would be best, but in most cases a silicon rectifier is adequate. Analog and Digital Grounds Extreme care must be taken to avoid ground loops in the layout of ICL7104 circuits, especially in 16-bit and high sen- sitivity circuits most important that return currents from PIN 35 I/P ...

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... ICL7104 with ICL8052/8068 Integrating A/D Converter Equations • Oscillator CRYSTAL or RC (RC on -14 Part Only) f (Typ) 200kHz OSC f = 0.45/RC (ICL7104-14 Only) OSC C > 50pF and R > 50K OSC OSC • Oscillator Period t = 1/f OSC OSC • Integration Clock Frequency CLOCK OSC • Integration Period ...