EM35X-DEV-UPG-IAR Ember, EM35X-DEV-UPG-IAR Datasheet - Page 130
EM35X-DEV-UPG-IAR
Manufacturer Part Number
EM35X-DEV-UPG-IAR
Description
IAR EWARM LICENCE FOR EM35X
Manufacturer
Ember
Type
Licenser
Specifications of EM35X-DEV-UPG-IAR
For Use With/related Products
EM35x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1028
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EM351 / EM357
Figure 9-5. Counter Timing Diagram, Update Event when TIM_ARBE = 0 (TIMx_ARR not buffered)
Figure 9-6. Counter Timing Diagram, Update Event when TIM_ARBE = 1 (TIMx_ARR buffered)
Down-Counting Mode
9.3.2.2
In down-counting mode, the counter counts from the auto-reload value (contents of the TIMx_ARR register)
down to 0, then restarts from the auto-reload value and generates a counter underflow event.
A UEV can be generated at each counter underflow, by setting the TIM_UG bit in the TIMx_EGR register, or by
using the slave mode controller. Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1
register, to avoid updating the shadow registers while writing new values in the buffer registers. No UEV
occurs until the TIM_UDIS bit is written to 0. However, the counter restarts from the current auto-reload
value, whereas the prescaler’s counter restarts from 0, but the prescale rate doesn’t change.
In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV, but
without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and
capture interrupts when clearing the counter on the capture event.
9-6
120-035X-000G
Final
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