HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 171
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HW-SPAR3E-SK-US-G
Manufacturer Part Number
HW-SPAR3E-SK-US-G
Description
KIT STARTER SPARTAN-3E
Manufacturer
Xilinx Inc
Specifications of HW-SPAR3E-SK-US-G
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1507
- XC3S100E-4VQG100C PDF datasheet
- HW-USB-G_PRODUCT_CHANGE PDF datasheet #2
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User I/Os by Bank
Table 132
distributed between the four I/O banks on the VQ100 pack-
age.
Table 132: User I/Os Per Bank for XC3S100E, XC3S250E, and XC3S500E in the VQ100 Package
Footprint Migration Differences
The production XC3S100E, XC3S250E, and XC3S500E
FPGAs have identical footprints in the VQ100 package.
Designs can migrate between the devices without further
consideration.
DS312-4 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Package
Edge
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
indicates how the 66 available user-I/O pins are
R
I/O Bank
0
1
2
3
Maximum
I/O
15
15
19
17
66
I/O
16
5
6
0
5
www.xilinx.com
INPUT
0
0
0
1
1
All Possible I/O Pins by Type
DUAL
18
21
1
0
2
VREF
1
1
1
1
4
(1)
Pinout Descriptions
CLK
0
24
8
8
8
(2)
(1)
171
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