HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 142

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

DC and Switching Characteristics
Block RAM Timing
Table 103: Block RAM Timing
142
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
T
Hold Times
T
T
T
T
Clock Timing
T
T
Clock Frequency
F
Symbol
BCKO
BACK
BDCK
BECK
BWCK
BCKA
BCKD
BCKE
BCKW
BPWH
BPWL
BRAM
The numbers in this table are based on the operating conditions set forth in
When reading from block RAM, the delay from the
active transition at the CLK input to data appearing at
the DOUT output
Setup time for the ADDR inputs before the active
transition at the CLK input of the block RAM
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
Setup time for the EN input before the active transition
at the CLK input of the block RAM
Setup time for the WE input before the active transition
at the CLK input of the block RAM
Hold time on the ADDR inputs after the active transition
at the CLK input
Hold time on the DIN inputs after the active transition at
the CLK input
Hold time on the EN input after the active transition at
the CLK input
Hold time on the WE input after the active transition at
the CLK input
High pulse width of the CLK signal
Low pulse width of the CLK signal
Block RAM clock frequency. RAM read output value
written back into RAM, for shift-registers and circular
buffers. Write-only or read-only performance is faster.
Description
www.xilinx.com
Table
0.33
0.23
0.67
1.09
0.12
0.12
1.39
1.39
Min
77.
0
0
0
-
-5
Max
2.45
270
Speed Grade
-
-
-
-
-
-
-
-
-
-
DS312-3 (v3.8) August 26, 2009
0.38
0.23
0.77
1.26
0.14
0.13
1.59
1.59
Min
0
0
0
-
-4
Product Specification
Max
2.82
230
-
-
-
-
-
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R