EVAL-ADM1026EB ON Semiconductor, EVAL-ADM1026EB Datasheet - Page 42

• Manufacturer Part Number: EVAL-ADM1026EB
• Description: BOARD EVAL FOR ADM1026
• Manufacturer: ON Semiconductor
• Type: Temperature Sensorr

Specifications of EVAL-ADM1026EB

• Contents: Evaluation Board
• For Use With/related Products: ADM1026
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 35. Register 19h, Mask Register 2 (Power−On Default, 00h)
Table 36. Register 1Ah, Mask Register 3 (Power−On Default, 00h)
Table 37. Register 1Bh, Mask Register 4 (Power−On Default, 00h)
Table 38. Register 1Ch, Mask Register 5 (Power−On Default, 00h)
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Int Temp Mask = 0
GPIO16 Mask = 0
THERM Mask = 0
GPIO0 Mask = 0
GPIO1 Mask = 0
GPIO2 Mask = 0
GPIO3 Mask = 0
GPIO4 Mask = 0
GPIO5 Mask = 0
GPIO6 Mask = 0
GPIO7 Mask = 0
FAN0 Mask = 0
FAN1 Mask = 0
FAN2 Mask = 0
FAN3 Mask = 0
FAN4 Mask = 0
FAN5 Mask = 0
FAN6 Mask = 0
FAN7 Mask = 0
V
AFC Mask = 0
A
A
A
A
A
A
A
A
A
CI Mask = 0
BAT
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
Unused
Name
Name
Name
Name
Mask = 0
Mask = 0
Mask = 0
Mask = 0
Mask = 0
Mask = 0
Mask = 0
Mask = 0
Mask = 0
Mask = 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated on the FAN0 tach channel are masked out.
When this bit is set, interrupts generated on the FAN1 tach channel are masked out.
When this bit is set, interrupts generated on the FAN2 tach channel are masked out.
When this bit is set, interrupts generated on the FAN3 tach channel are masked out.
When this bit is set, interrupts generated on the FAN4 tach channel are masked out.
When this bit is set, interrupts generated on the FAN5 tach channel are masked out.
When this bit is set, interrupts generated on the FAN6 tach channel are masked out.
When this bit is set, interrupts generated on the FAN7 tach channel are masked out.
When this bit is set, interrupts generated on the internal temperature channel are
masked out.
When this bit is set, interrupts generated on the V
When this bit is set, interrupts generated on the A
When this bit is set, interrupts generated from THERM events are masked out.
When this bit is set, interrupts generated from automatic fan control events are
masked out.
Unused. Reads back 0.
When this bit is set, interrupts generated by the chassis intrusion input are masked out.
When this bit is set, interrupts generated on the GPIO16 channel are masked out.
When this bit is set, interrupts generated on the GPIO0 channel are masked out.
When this bit is set, interrupts generated on the GPIO1 channel are masked out.
When this bit is set, interrupts generated on the GPIO2 channel are masked out.
When this bit is set, interrupts generated on the GPIO3 channel are masked out.
When this bit is set, interrupts generated on the GPIO4 channel are masked out.
When this bit is set, interrupts generated on the GPIO5 channel are masked out.
When this bit is set, interrupts generated on the GPIO6 channel are masked out.
When this bit is set, interrupts generated on the GPIO7 channel are masked out.
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42
Description
Description
Description
Description
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
BAT
IN8
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.
voltage channel are masked out.