SI3210DCQ1-EVB Silicon Laboratories Inc, SI3210DCQ1-EVB Datasheet - Page 115

• Manufacturer Part Number: SI3210DCQ1-EVB
• Description: DAUGHTERCARD W/SI3201 INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r
• Type: SLIC/CODECr

Specifications of SI3210DCQ1-EVB

• Contents: Evaluation Board and CD-ROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Si3210
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
Addr.
Addr. D15
*Note: Si3210 only.
28
29
30
31
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
and written but should be written to zeroes.
Loop Closure Threshold.
Loop closure detection threshold. This register defines the upper bounds threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
Ring Trip Threshold.
Ring trip detection threshold during ringing.
Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
Common Mode Maximum Threshold for Speed-Up.
This register defines the positive common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
D14
D13
Table 44. SLIC Control Indirect Registers Description
Table 43. SLIC Control Indirect Registers Summary
LCRTL[5:0]
D12
RPTP[5:0]
LCRT[5:0]
VMIND[3:0]*
PPT12[7:0]
PPT34[7:0]
PPT56[7:0]
VCMR[3:0]
D11
D10
CMH[5:0]
CML[5:0]
NCLR[12:0]
NRTP[12:0]
NQ12[12:0]
NQ34[12:0]
NQ56[12:0]
Description
D9
Rev. 1.42
D8
D7
D6
D5
Si3210/Si3211
D4
D3
D2
Reference Page
D1
29
39
D0
115