SI3210DCQ1-EVB Silicon Laboratories Inc, SI3210DCQ1-EVB Datasheet
SI3210DCQ1-EVB
Specifications of SI3210DCQ1-EVB
Related parts for SI3210DCQ1-EVB
SI3210DCQ1-EVB Summary of contents
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P SLIC Features Performs all BORSCHT functions Software programmable internal ...
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Si3210/Si3211 2 Rev. 1.42 ...
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Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . ...
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Si3210/Si3211 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage 2 Operating Temperature Range Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical 2 ...
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Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3210/11 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply ...
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Si3210/Si3211 Table 3. AC Characteristics (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Gain Variation with Temperature Gain Variation with Supply ...
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Figure 1. Transmit and Receive Path SNDR Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance Rev. 1.42 Si3210/Si3211 Acceptable ...
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Si3210/Si3211 Figure 3. Transmit Path Frequency Response 8 Typical Response Typical Response Rev. 1.42 ...
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Figure 4. Receive Path Frequency Response Rev. 1.42 Si3210/Si3211 9 ...
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Si3210/Si3211 Figure 5. Transmit Group Delay Distortion 10 Figure 6. Receive Group Delay Distortion Rev. 1.42 ...
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Table 4. Linefeed Characteristics ( 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol Loop Resistance Range R LOOP DC Loop Current Accuracy DC Open ...
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Si3210/Si3211 Table 5. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity ...
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Table 8. Power Supply Characteristics ( 3. 5. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Power Supply Current Analog and Digital ...
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Si3210/Si3211 Table 9. Switching Characteristics—General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: ...
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Table 10. Switching Characteristics—SPI 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK ...
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Si3210/Si3211 Table 11. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for K-Grade, – °C for B-Grade Parameter PCLK Frequency PCLK Duty Cycle Tolerance PCLK Period ...
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TIP C5 22nF Protection Circuit C6 22nF 3 RING Notes: 1. Values and configurations for these components can be derived from Table 19 or from App Note 45. 2. Only one component per system needed. R21 3. All circuit ...
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Si3210/Si3211 SDCH SDCL DCFF DCDRV Notes: 1. Values and configurations for these components can be derived 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 10. Si3210 BJT/Inductor DC-DC Converter Circuit Table 13. Si3210 BJT/Inductor DC-DC ...
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Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C14* C25* 10 µF, Electrolytic, ±20% C27 470 pF, 100 V, X7R, ±20% R17 R18 1/4 W, ...
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Si3210/Si3211 TIP Protection Circuit RING Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single-point connection to the ground plane. 3. Si3201 bottom-side exposed pad should be electrically ...
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Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF Protection Circuit R6 C6 80.6 22nF RING Notes: 1. Values and configurations for these components can be derived from Table 19 or from App Note 45. 2. Only one ...
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Si3210/Si3211 Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF Protection Circuit R6 C6 80.6 22nF RING Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single-point connection to the ground plane. ...
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RRE Figure 15. Si321x Optional Equivalent Q5, Q6 Bias Circuit Table 18. Si321x Optional Bias Component Values Component 100 nF, 100 V, X7R, ±20% C7,C8 3.0 kΩ, 1/10 W, ±5% R23,R24 The subcircuit above can be substituted into any of ...
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Si3210/Si3211 2. Functional Description ® The ProSLIC is a single low-voltage CMOS device that provides all the SLIC, codec, DTMF detection, and signal generation functions needed for a complete analog telephone interface. The ProSLIC performs all battery, overvoltage, ringing, supervision, ...
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Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure simplified illustration of the ...
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Si3210/Si3211 Audio Codec A/D D/A AC Control AC Sense Control Loop TIP or RING Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 23. ProSLIC Linefeed Operations LF[2:0]* Linefeed State ...
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Table 24. Measured Realtime Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – V TIP RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense BAT Transistor ...
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Si3210/Si3211 Table 25. Associated Power Monitoring and Power Fault Registers Parameter Power Monitor Pointer Line Power Monitor Output Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 ...
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LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during on-hook transmission or on- hook active states. The ProSLIC performs loop closure detection digitally using ...
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Si3210/Si3211 2.1.9. Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset. It ...
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MOSFET/Transformer Circuit Option Using Si3210M The MOSFET/transformer circuit option, as defined in Figure 11, offers higher power efficiencies across a larger input voltage range. Depending transformers primary inductor value and the switching frequency, the input voltage (V ) can ...
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Si3210/Si3211 to determine whether there is any other off-hook terminal equipment on the same line. TRACK = 0 mode is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds) and cannot ...
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DC-DC Converter Enhancements Silicon revisions C and higher enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting ...
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Si3210/Si3211 8 kHz Clock OnE Zero 16-Bit Cross OAT Modulo Logic Expire Counter OIT Expire OATn OATnE OITn OITnE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 20. Simplified Tone Generator ...
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The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures that ...
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Si3210/Si3211 O1E ... ... 0 AT1 OSS1 Tone Gen. 1 Signal Output Figure 21. Tone Generator Timing Diagram 2.3.4. Enhanced FSK Waveform Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by ...
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Table 30. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage ...
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Si3210/Si3211 2.4.3. Trapezoidal Ringing In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal illustrates a trapezoidal ringing waveform with offset V . ROFF V TIP-RING V ROFF T=1/freq t RISE Figure 22. Trapezoidal Ringing Waveform To configure the ...
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OVR LOAD , PK β β where is the minimum expected current gain of transistors Q5 and Q6. The minimum value for VBATH is therefore given by ...
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Si3210/Si3211 Table 31. Associated Registers for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses ...
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Table 33. Associated Pulse Metering Generator Registers Parameter Pulse Metering Frequency Coefficient Pulse Metering Amplitude Coefficient Pulse Metering Attack/Decay Ramp Rate Pulse Metering Active Timer Pulse Metering Inactive Timer Pulse Metering Control Status and control registers Note: The ProSLIC uses ...
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Si3210/Si3211 overwritten by a new one. There is no buffering of the digit information. 2.7. Audio Path Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loop-back modes. The ...
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Si3210/Si3211 Rev. 1.42 43 ...
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Si3210/Si3211 2.7.2. Receive Path In the receive path, the optionally compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16-bit word. ...
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An additional analog loopback (ALM1) takes the digital stream at the output of the A/D converter and feeds it back to the D/A converter. (See Figure 25.) The signal path starts with the analog signal at the input of the ...
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Si3210/Si3211 The interface to the interrupt logic consists of six registers. Three interrupt status registers contain 1 bit for each of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource. Three ...
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SCLK CS SDI SDO Figure 26. Serial Write 8-Bit Mode SCLK CS SDI SDO High Impedance Figure 27. Serial Read 8-Bit Mode Don't Care ...
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Si3210/Si3211 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – ...
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PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM Mode Select (direct Register 1), ...
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Si3210/Si3211 PCLK FSYNC PCLK_CNT 0 1 DRX DTX HI-Z Figure 31. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) PCLK FSYNC PCLK_CNT 0 1 DRX MSB DTX HI-Z Figure 32. GCI Example, Timeslot 1 (TXS/RXS = 0) 2.13. ...
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Table 34. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Si3210/Si3211 Table 35. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 ...
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Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count—Low Byte 3 PCM Transmit Start Count—High Byte 4 PCM ...
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Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 28 Indirect Data Access— Low Byte 29 Indirect Data Access— High Byte 30 Indirect Address 31 Indirect Address Status 32 Oscillator 1 Control 33 Oscillator 2 Control 34 Ringing Oscillator Control ...
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Table 36. Direct Register Summary (Continued) Register Name 46 Pulse Metering Oscillator Inactive Timer—Low Byte 47 Pulse Metering Oscillator Inactive Timer—High Byte 48 Ringing Oscillator Active Timer—Low Byte 49 Ringing Oscillator Active Timer—High Byte 50 Ringing Oscillator Inac- tive Timer—Low ...
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Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 77 Line Power Output Monitor 78 Loop Voltage Sense 79 Loop Current Sense 80 TIP Voltage Sense 81 RING Voltage Sense 82 Battery Voltage Sense 1 83 Battery Voltage Sense 2 ...
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Table 36. Direct Register Summary (Continued) Register Name 101 Common Mode Loop Current Gain Calibration Result 102 Current Limit Calibration Result 103 Monitor ADC Offset Calibration Result 104 Analog DAC/ADC Offset 105 DAC Offset Calibration Result 106 Common Mode Balance ...
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Si3210/Si3211 Register 0. SPI Mode Select Bit D7 D6 Name SPIDC SPIM Type R/W R/W Reset settings = 00xx_xxxx Bit Name 7 SPIDC SPI Daisy Chain Mode Enable Disable SPI daisy chain mode Enable SPI daisy ...
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Register 1. PCM Mode Select Bit D7 D6 Name PCME Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5 PCME PCM Enable Disable PCM transfers Enable PCM transfers. 4:3 PCMF[1:0] PCM Format. ...
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Si3210/Si3211 Register 3. PCM Transmit Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 TXS[9:8] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following ...
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Register 6. Digital Input/Output Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 DOUT DOUT Pin Output Data (Si3211 only ...
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Si3210/Si3211 Register 8. Audio Path Loopback Control Bit D7 D6 Name Type Reset settings = 0000_0010 Bit Name 7:3 Reserved Read returns zero. 2 ALM2 Analog Loopback Mode 2. (See Figure 25 on page 43 Full analog loopback ...
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Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF HPF bypassed ...
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Si3210/Si3211 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...
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Register 11. Hybrid Control Bit D7 D6 Name HYBP[2:0] Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 ...
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Si3210/Si3211 Register 14. Powerdown Control 1 Bit D7 D6 Name PMON Type Reset settings = 0001_0000 Bit D7 D6 Name PMON Type Reset settings = 0001_0000 Bit Name 7:6 Reserved Read returns zero. 5 PMON Pulse Metering DAC Power-On Control. ...
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Register 15. Powerdown Control 2 Bit D7 D6 Name ADCM Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual power ...
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Si3210/Si3211 Register 18. Interrupt Status 1 Bit D7 D6 Name PMIP PMAP RGIP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIP Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 ...
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Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Si3210/Si3211 Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCP Common Mode Calibration Error Interrupt. This bit is set when off-hook/on-hook status changes during the common ...
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Register 21. Interrupt Enable 1 Bit D7 D6 Name PMIE PMAE RGIE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIE Pulse Metering Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 6 PMAE Pulse ...
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Si3210/Si3211 Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power ...
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Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCE Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE Indirect ...
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Si3210/Si3211 Register 24. DTMF Decode Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 VAL DTMF Valid Digit Decoded Not currently detecting digit Currently detecting digit. 3:0 ...
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Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into ...
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Si3210/Si3211 Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect ...
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Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator 1 ...
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Si3210/Si3211 Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. ...
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Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved ...
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Si3210/Si3211 Register 35. Pulse Metering Oscillator Control Bit D7 D6 Name PSTAT Type R Reset settings = 0000_0000 Bit Name 7 PSTAT Pulse Metering Signal Status Output signal inactive Output signal active. 6:5 Reserved Read returns ...
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Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type ...
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Si3210/Si3211 Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = ...
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Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type ...
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Si3210/Si3211 Register 45. Pulse Metering Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PAT[15:8] Pulse Metering Active Timer. Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset ...
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Register 48. Ringing Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[7:0] Ringing Active Timer. LSB = 125 µs Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset ...
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Si3210/Si3211 Register 51. Ringing Oscillator Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[15:8] Ringing Inactive Timer. Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 ...
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Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual realtime linefeed state. Automatic operations may cause actual linefeed state ...
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Si3210/Si3211 Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. ...
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Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit D7 D6 Name Type Reset settings = 0000_0110 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. (Si3210 only; See Figure ...
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Si3210/Si3211 Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which ...
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Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the realtime output of ring ...
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Si3210/Si3211 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum ...
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Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity ...
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Si3210/Si3211 Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be ...
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Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the ...
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Si3210/Si3211 Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage ...
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Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the realtime voltage at TIP with respect to ground. The range (0x00) to ...
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Si3210/Si3211 Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage ground. ...
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Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the realtime current through Q3. The range (0x00) to 9.59 mA ...
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Si3210/Si3211 Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the realtime current through Q6. The range (0x00) to 80.58 ...
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Register 93. DC-DC Converter Switching Delay Bit D7 D6 Name DCCAL DCPOL Type R/W Reset settings = 0001_0100 (Si3210) Reset settings = 0011_0100 (Si3210M) Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7 DCCAL DC-DC Converter Peak ...
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Si3210/Si3211 Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width (Si3210 only). Pulse width of DCDRV ...
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Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL CALSP Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 ...
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Si3210/Si3211 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled ...
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Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. Register 99. TIP Gain Mismatch Calibration ...
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Si3210/Si3211 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result ...
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Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ...
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Si3210/Si3211 Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:4 Reserved Read returns zero. 3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result. 108 Function Rev. 1.42 ...
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Register 108. Enhancement Enable Note: The Enhancement Enable register and associated features are available in silicon revisions C and later. Bit D7 D6 Name ILIMEN FSKEN DCSU Type R/W R/W Reset settings = 0000_0000 Bit D7 D6 Name ILIMEN FSKEN ...
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Si3210/Si3211 Bit Name 4 ZSEXT Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize ac impedances for 600 + 2.1 µF and 900 + 2.16 µF so that an external resistor reference ...
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Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. ...
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Si3210/Si3211 Table 38. DTMF Indirect Registers Description (Continued) Addr. 2 DTMF Row 2 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 2 DTMF detection. If the ratio of power in row 2 to ...
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Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded ...
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Si3210/Si3211 Table 40. Oscillator Indirect Registers Description (Continued) Addr. 20 Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. 21 Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. 22 Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator ...
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SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote ...
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Si3210/Si3211 Table 44. SLIC Control Indirect Registers Description (Continued) Addr. 32 Power Alarm Threshold for Transistors Q1 and Q2. 33 Power Alarm Threshold for Transistors Q3 and Q4. 34 Power Alarm Threshold for Transistors Q5 and Q6. 35 Loop Closure ...
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Table 46. FSK Control Indirect Registers Description Addr. 99 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a space or “0”. When the active ...
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Si3210/Si3211 5. Pin Descriptions: Si3210/11 QFN DTX FSYNC 2 RESET 3 SDCH/DIO1 4 SDCL/DIO2 DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC ...
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QFN TSSOP Name Pin # Pin # 5 9 SDCL/DIO2 DC Monitor/General Purpose I/O. DC-DC converter monitor input used to detect overcurrent situations in the converter (Si3210 only). General purpose I/O (Si3211 only VDDA1 Analog Supply Voltage. Analog ...
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Si3210/Si3211 QFN TSSOP Name Pin # Pin # 23 27 VDDA2 24 28 ITIPP 25 29 ITIPN 26 30 VDDD 27 31 GNDD 28 32 TEST 29 33 DCFF/DOUT 30 34 DCDRV/DCSW DC Drive/Battery Switch SDITHRU 32 36 ...
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Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O 13 ...
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Si3210/Si3211 7. Ordering Guide Chip Description DC-DC Converter Si3210-FM ProSLIC Si3210-GM ProSLIC Si3210M-FM ProSLIC Si3210M-GM ProSLIC Si3210-KT ProSLIC Si3210-BT ProSLIC Si3210-FT ProSLIC Si3210-GT ProSLIC Si3210M-KT ProSLIC Si3210M-BT ProSLIC Si3210M-FT ProSLIC Si3210M-GT ProSLIC Si3211-KT ProSLIC Si3211-BT ProSLIC Si3201-KS Linefeed Interface Si3201-BS ...
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... Table 47. Evaluation Kit Ordering Guide Item Supported ProSLIC Si3210PPQX-EVB Si3210-QFN Si3210PPQ1-EVB Si3210-QFN Si3210DCQX-EVB Si3210-QFN Si3210DCQ1-EVB Si3210-QFN Si3210PPTX-EVB Si3210-TSSOP Si3210PPT1-EVB Si3210-TSSOP Si3210DCX-EVB Si3210-TSSOP Si3210DC1-EVB Si3210-TSSOP Si3210MPPTX-EVB Si3210M-TSSOP Si3210MPPT1-EVB Si3210M-TSSOP Si3210MDCX-EVB Si3210M-TSSOP Si3210MDC1-EVB Si3210M-TSSOP Si3211PPTX-EVB Si3211-TSSOP Si3210/Si3211 Description Eval Board, Daughter Card Eval Board, Daughter Card ...
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Si3210/Si3211 8. Product Identification The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number. Example: Si3210-X-FM Part designator: temperature, packing, product, etc. Part revision ...
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Package Outline: 38-Pin QFN Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the illustration. Figure 33. 38-Pin Quad Flat No-Lead Package (QFN) Table 48. Package Diagram Dimensions Symbol ...
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Si3210/Si3211 10. Package Outline: 38-Pin TSSOP Figure 34 illustrates the package details for the Si321x. Table 49 lists the values for the dimensions shown in the illustration. E/2 2x ddd aaa C Seating Plane C ...
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Package Outline: 16-Pin ESOIC Figure 35 illustrates the package details for the Si3201. Table 50 lists the values for the dimensions shown in the illustration . –A– Seating ...
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Si3210/Si3211 OCUMENT HANGE IST Revision 1.41 to Revision 1.42 16-pin ESOIC dimension A1 corrected in Table 49 on page 126. Delay time between chip selects, t 220 ns to 440 ns in Table 10 on page 15. ...
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N : OTES Si3210/Si3211 Rev. 1.42 129 ...
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