HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 213

• Manufacturer Part Number: HS7750KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3. Low-Power Modes (Sleep, Standby, and Module Standby)
Notes: 1. After the sleep mode is cleared by a break, execution restarts at the instruction
4. RESET Signals (/RESET and /MRESET)
Note: Do not start user program execution while control input signals (/RESET, /RDY, and
5. Direct Memory Access Controller (DMAC)
6. Internal I/O Registers
Note: As default, SDMR2 and SDMR3 are specified in the I/O-register definition file as the
For low-power consumption, the SH7750 and SH7750S have sleep, standby, and module
standby modes.
The sleep and standby modes are switched using the SLEEP instruction. When the emulator is
used, the sleep mode can be cleared by either normal clearing or by the satisfaction of a break
condition (including (BREAK) or (CTRL) + C key input). In the latter case, the user program
breaks. The standby mode can be cleared with the normal clearing function or (BREAK) or
(CTRL) + C key input, and after the standby mode is cleared, the user program operates
correctly. Note, however, that if a command has been entered in standby mode or module
standby mode, no commands can be used from the emulator after the standby mode is cleared.
The SH7750 and SH7750S RESET signals (/RESET and /MRESET) are only valid during user
program execution started with clicking the GO or STEP-type button. If these signals are
input from the user system in command input wait state, they are not sent to the SH7750 or
SH7750S.
The DMAC operates even in the command wait state. When a data transfer request is
generated, the DMAC executes DMA transfer.
In the emulator, the internal I/O registers can be accessed from the [I/O registers] window.
However, pay attention when accessing the SDMR register of the bus-state controller. Before
accessing the SDMR register, specify addresses to be accessed in the I/O-register definition
file (SH7750.IO or SH7750S.IO) and then activate the HDI. For details on I/O-register
definition files, refer to the Hitachi Debugging Interface User's Manual.
When the SH7750S is used, the IPRD register is not displayed in the [I/O Registers] window.
To get it to display, edit the I/O-register definition file (SH7750.IO) as follows and start the
HDI:
2. If the memory is accessed or modified in sleep mode, the sleep mode is cleared and
3. Although the SH7750S supports the hardware standby function, if the SH7750
/BREQ) are being low. A TIMEOUT error will occur.
area-2 SDMR register and area-3 SDMR register, respectively.
following the SLEEP instruction.
execution starts at the instruction following the SLEEP instruction.
E10A emulator enters the hardware standby mode, a TIMEOUT error will occur.
Rev. 2.0, 01/01, page 189 of 214