C8051F124-TB Silicon Laboratories Inc, C8051F124-TB Datasheet - Page 43

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C8051F124-TB

Manufacturer Part Number
C8051F124-TB
Description
BOARD PROTOTYPING W/C8051F124
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of C8051F124-TB

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AIN2.0/A8/P1.0
AIN2.1/A9/P1.1
ALE/P0.5
WR/P0.7
RD/P0.6
Name
DAC1
P0.0
P0.1
P0.2
P0.3
P0.4
‘F120
‘F122
‘F124
‘F126
99
62
61
60
59
58
57
56
55
36
35
Pin Numbers
‘F121
‘F123
‘F125
‘F127
63
55
54
53
52
51
50
49
48
29
28
Table 4.1. Pin Definitions (Continued)
‘F130
‘F132
62
61
60
59
58
57
56
55
36
35
‘F131
‘F133
55
54
53
52
51
50
49
48
29
28
Rev. 1.4
A Out Digital to Analog Converter 1 Voltage Output.
D I/O Port 0.0. See Port Input/Output section for com-
D I/O Port 0.1. See Port Input/Output section for com-
D I/O Port 0.2. See Port Input/Output section for com-
D I/O Port 0.3. See Port Input/Output section for com-
D I/O Port 0.4. See Port Input/Output section for com-
D I/O ALE Strobe for External Memory Address bus
D I/O /RD Strobe for External Memory Address bus
D I/O /WR Strobe for External Memory Address bus
D I/O
D I/O
Type
A In
A In
C8051F120/1/2/3/4/5/6/7
(See DAC Specification for complete descrip-
tion).
plete description.
plete description.
plete description.
plete description.
plete description.
(multiplexed mode)
Port 0.5
See Port Input/Output section for complete
description.
Port 0.6
See Port Input/Output section for complete
description.
Port 0.7
See Port Input/Output section for complete
description.
ADC2 Input Channel 0 (See ADC2 Specification
for complete description).
Bit 8 External Memory Address bus (Non-multi-
plexed mode)
Port 1.0
See Port Input/Output section for complete
description.
Port 1.1. See Port Input/Output section for com-
plete description.
C8051F130/1/2/3
Description
43

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