C8051F124-TB Silicon Laboratories Inc, C8051F124-TB Datasheet - Page 205
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C8051F124-TB
Manufacturer Part Number
C8051F124-TB
Description
BOARD PROTOTYPING W/C8051F124
Manufacturer
Silicon Laboratories Inc
Specifications of C8051F124-TB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Flash Read Lock Byte
Bits7–0: Each bit locks a corresponding block of memory. (Bit7 is MSB).
Flash Write/Erase Lock Byte
Bits7–0: Each bit locks a corresponding block of memory.
Flash access Limit Register (FLACL)
Read and Write/Erase Security Bits.
(Bit 7 is MSB.)
Bit
7
6
5
4
3
2
1
0
0x0C000 - 0x0FFFF
0x08000 - 0x0BFFF
0x04000 - 0x07FFF
0x00000 - 0x03FFF
Memory Block
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG inter-
face.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG
interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG
interface.
NOTE: When the highest block is locked, the security bytes may be written but not erased.
The Flash Access Limit is defined by the setting of the FLACL register, as described in SFR
Definition 15.1. Firmware running at or above this address is prohibited from using the
MOVX and MOVC instructions to read, write, or erase Flash locations below this address.
Figure 15.3. 64 kB Flash Memory Map and Security Bytes
N/A
N/A
N/A
N/A
Write/Erase Lock Byte
Read Lock Byte
Memory Space
Program/Data
SFLE = 0
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
0x0FFFF
0x0FFFE
0x0FFFD
0x00000
Flash Access Limit
C8051F130/1/2/3
Scratchpad Memory
SFLE = 1
(Data only)
0x00FF
0x0000
205
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