DSP56F801EVM Freescale Semiconductor, DSP56F801EVM Datasheet - Page 44

• Manufacturer Part Number: DSP56F801EVM
• Description: KIT EVALUATION FOR DSP56F801
• Manufacturer: Freescale Semiconductor

Specifications of DSP56F801EVM

• Processor To Be Evaluated: 56F801
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation:
44
•
•
•
•
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (T
determined by a thermocouple.
Provide a low-impedance path from the board power supply to each V
board ground to each V
The minimum bypass requirement is to place 0.1 μF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the ten V
performance tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
pins are less than 0.5 inch per capacitor lead.
DD
/V
SS
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
pairs, including V
SS
(GND) pin.
56F801 Technical Data, Rev. 17
DDA
/V
J
SSA.
CAUTION
– T
T
Ceramic and tantalum capacitors tend to provide better
)/P
D
where T
T
is the temperature of the package case
DD
pin on the controller, and from the
Freescale Semiconductor
DD
and V
SS
(GND)