DSP56F801EVM Freescale Semiconductor, DSP56F801EVM Datasheet - Page 11

• Manufacturer Part Number: DSP56F801EVM
• Description: KIT EVALUATION FOR DSP56F801
• Manufacturer: Freescale Semiconductor

Specifications of DSP56F801EVM

• Processor To Be Evaluated: 56F801
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.4 Interrupt and Program Control Signals
2.5 Pulse Width Modulator (PWM) Signals
Freescale Semiconductor
No. of
No. of
No. of
Pins
Pins
Pins
6
1
1
1
1
GPIOB3
PWMA0-5
FAULTA0
RESET
Signal
Signal
Name
Name
XTAL
IRQA
Signal
Name
(Schmitt)
(Schmitt)
Signal
Output
Output
Signal
Input/
Type
Type
Input
Input
(Schmitt)
Signal
Output
Type
Input
Table 2-7 Pulse Width Modulator (PWMA) Signals
Table 2-6 Interrupt and Program Control Signals
During Reset
During Reset
Table 2-5 PLL and Clock (Continued)
driven
State
Chip-
Input
State During
State
Input
Input
Tri-stated
Reset
Input
56F801 Technical Data, Rev. 17
Crystal Oscillator Output—This output should be connected to an 8MHz
external crystal or ceramic resonator. For more information, please refer to
Section
This pin can also be connected to an external clock source. For more
information, please refer to
Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that
can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the XTAL pin is not needed.
External Interrupt Request A—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered.
Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
PWMA0-5— These are six PWMA output pins.
FAULTA0— This fault input pin is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.
3.5.
Section
Signal Description
Signal Description
Signal Description
3.5.3.
Interrupt and Program Control Signals
11