DSP56F801EVM Freescale Semiconductor, DSP56F801EVM Datasheet - Page 18

• Manufacturer Part Number: DSP56F801EVM
• Description: KIT EVALUATION FOR DSP56F801
• Manufacturer: Freescale Semiconductor

Specifications of DSP56F801EVM

• Processor To Be Evaluated: 56F801
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

18
V
Low Voltage Interrupt, external power supply
Low Voltage Interrupt, internal power supply
Power on Reset
1. Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.
2. Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.
3. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
4. PWM pin output source current measured with 50% duty cycle.
5. PWM pin output sink current measured with 50% duty cycle.
6. I
7. Run (operating) I
inputs; measured with all modules enabled.
8. Wait I
less than 50pF on all outputs. C
measured with PLL enabled.
9. This low voltage interrupt monitors the V
via separate traces. If V
conditions when V
10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below V
unless the external power supply drops below the minimum specified value (3.0V).
11. Power
up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The
internally regulated voltage is typically 100 mV less than V
DD
supply current
DDT
Run
Wait
Stop
Run
= I
Operating Conditions:
DD
–
7
7
8
DD
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping
(60MHz operation)
(80MHz operation)
measured using external square wave clock source (f
EIC
+ I
11
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated
DDA
DDA
DD
(Total supply current for V
>V
DDA
Table 3-4 DC Electrical Characteristics (Continued)
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as
EIO
Characteristic
drops below V
(between the minimum specified V
L
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait I
V
EIO
SS
DDA
, an interrupt is generated. Functionality of the device is guaranteed under transient
= V
56F801 Technical Data, Rev. 17
DD
10
external power supply. V
9
SSA
+ V
= 0 V, V
DDA
DD
)
during ramp up until 2.5V is reached, at which time it self regulates.
DD
DD
= V
and the point when the V
osc
DDA
= 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads;
DDA
= 3.0–3.6V, T
Symbol
is generally connected to the same potential as V
I
V
V
V
DDT
POR
EIO
EIC
6
A
EIO
= –40° to +85°C, C
interrupt is generated).
Min
2.4
2.0
—
—
—
—
—
Freescale Semiconductor
Typ
120
102
2.7
2.2
1.7
96
62
L
≤
50pF
Max
130
111
102
3.0
2.4
2.0
70
DD
DD
Unit
mA
mA
mA
mA
V
V
V
;