KS8721SL-EVAL Micrel Inc, KS8721SL-EVAL Datasheet - Page 26

• Manufacturer Part Number: KS8721SL-EVAL
• Description: BOARD EVAL EXPERIMENT KS8721SL
• Manufacturer: Micrel Inc

Specifications of KS8721SL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8721SL
• Primary Attributes: 1 Port, 100BASE-TX/100BASE-FX/10BASE-T
• Secondary Attributes: MII, RMII, Auto MDI, MDIX, >130 Meter Cable Driver, LDO, IEEE802.3u Compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1010

KS8721BL/SL (3.3V Single Power Supply 10/100BaseTX/FX MII Physical Layer Transceiver)
RMII Signal Definition
Note: Unused MII signals, TXD[3:2], TXER need to tie to GND when RMII is
Reference Clock (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference
for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_ER. REF_CLK is sourced
by the MAC or an external source. Switch implementations may choose to
provide REF_CLK as an input or an output depending on whether they
provide a REF_CLK output or rely on an external clock distribution device.
Each PHY device shall have an input corresponding to this clock but may
use a single clock input for multiple PHYs implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the
criteria relevant to the operating mode. That is, in 10BASE-T mode, when
squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in
10 bits are detected carrier is said to be detected.
Loss of carrier shall result in the de-assertion of CRS_DV synchronous to
REF_CLK. So long as carrier criteria are being met, CRS_DV shall remain
asserted continuously from the first recovered di-bit of the frame through
the final recovered di-bit and shall be negated prior to the first REF_CLK
that follows the final di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted.
However, since the assertion of CRS_DV is asynchronous relative to
REF_CLK, the data on RXD[1:0] shall be "00" until proper receive signal
decoding takes place (see definition of RXD[1:0] behavior).
REF_CLK
CRS_DV
RXD[1:0]
TX_EN
TXD[1:0]
RX_ER
Signal
Name
using.
Direction
(with respect
to the PHY)
Output
Output
Output
Input
Input
Input
Direction
(with respect
to the MAC)
Input or Output
(Not Required)
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Output
Output
Input
Input
Input
Carrier Sense/Receive Data Valid
Synchronous clock reference for
KS8721BL/SL Preliminary Rev 0.90
receive, transmit and control
Transit Enable
Receive Error
Receive Data
Transit Data
interface
Use
Aug, 2003