KS8721SL-EVAL Micrel Inc, KS8721SL-EVAL Datasheet - Page 25

• Manufacturer Part Number: KS8721SL-EVAL
• Description: BOARD EVAL EXPERIMENT KS8721SL
• Manufacturer: Micrel Inc

Specifications of KS8721SL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8721SL
• Primary Attributes: 1 Port, 100BASE-TX/100BASE-FX/10BASE-T
• Secondary Attributes: MII, RMII, Auto MDI, MDIX, >130 Meter Cable Driver, LDO, IEEE802.3u Compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1010

KS8721BL/SL (3.3V Single Power Supply 10/100BaseTX/FX MII Physical Layer Transceiver)
RMII (Reduced MII) Data Interface
RMII interface specifies a low pin count (Reduced) Media Independent
Interface (RMII) intended for use between Ethernet PHYs and Switch or
Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
1. It is capable of supporting 10Mb/s and 100Mb/s data rates
2. A single clock reference is sourced from the MAC to PHY (or from an
3. It provides independent 2 bit wide (di-bit) transmit and receive data
4. It uses TTL signal levels, compatible with common digital CMOS ASIC
Error Signals: Whenever the KS8721BL/SL receives an error
symbol from the network, it asserts RXER and drives “1110” (4B) on
the RXD pins. When the MAC asserts TXER, the KS8721BL/SL will
drive “H” symbols (a Transmit Error define in the IEEE 802.3 4B/5B
code group) out on the line to force signaling errors.
Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter,
or /J/K symbol pair causes assertion of Carrier Sense (CRS). An
end-of-stream delimiter, or /T/R symbol pair causes de-assertion of
CRS. The PMA layer will also de-assert CRS if IDLE symbols are
received without /T/R, yet in this case RXER will be asserted for one
clock cycle when CRS is de-asserted. For 10T links, CRS assertion is
based on reception of valid preamble, and de-assertion on reception
of an end-of-frame (EOF) marker.
Collision: Whenever the line state is half-duplex and the
transmitter and receiver are active at the same time, the
KS8721BL/SL asserts its collision signal, which is asynchronous to
any clock.
external source)
paths
processes
For 100BaseTX link with the MII in 4B mode, RXDV is
asserted from the first nibble of the preamble to the last
nibble of the data packet.
For 10BaseT links, the entire preamble is truncated. RXDV
is asserted with the first nibble of the SFD “ 5D” and
remains asserted until the end of the packet.
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KS8721BL/SL Preliminary Rev 0.90
Aug, 2003