KS8721SL-EVAL Micrel Inc, KS8721SL-EVAL Datasheet - Page 24

• Manufacturer Part Number: KS8721SL-EVAL
• Description: BOARD EVAL EXPERIMENT KS8721SL
• Manufacturer: Micrel Inc

Specifications of KS8721SL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8721SL
• Primary Attributes: 1 Port, 100BASE-TX/100BASE-FX/10BASE-T
• Secondary Attributes: MII, RMII, Auto MDI, MDIX, >130 Meter Cable Driver, LDO, IEEE802.3u Compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1010

KS8721BL/SL (3.3V Single Power Supply 10/100BaseTX/FX MII Physical Layer Transceiver)
MII Data Interface
The INTPRT pin functions as a management data interrupt in the MII.
An active Low or High in this pin indicates a status change on the
KS8721BL/SL based on 1fh.9 level control. Register bits at 1bh[15:8]
are the interrupt enable bits. Register bits at 1bh[7:0] are the
interrupt condition bits. This interrupt is cleared by reading Register
1bh.
The data interface consists of separate channels for transmitting data
from a 10/100 802.3 compliant Media Access Controller (MAC) to the
KS8721BL/SL, and for receiving data from the line. Normal data
transmission is implemented in 4B Nibble Mode (4-bit wide nibbles).
Transmit Clock (TXC): The transmit clock is normally generated
by the KS8721BL/SL from an external 25MHz reference source at the
X1 input. The transmit data and control signals must always be
synchronized to the TXC by the MAC. The KS8721BL/SL normally
samples these signals on the rising edge of the TXC.
Receive Clock (RXC): For 100BaseTX links, the receive clock is
continuously recovered from the line. If the link goes down, and
auto-negotiation is disabled, the receive clock operates off the
master input clock (X1 or TXC). For 10BaseT links, the receive clock
is recovered from the line while carrier is active, and operates from
the master input clock when the line is idle. The KS8721BL/SL
synchronizes the receive data and control signals on the falling edge
of RXC in order to stabilize the signals at the rising edge of the clock
with 10ns setup and hold times.
Transmit Enable: The MAC must assert TXEN at the same time as
the first nibble of the preamble, and de-assert TXEN after the last bit
of the packet.
Receive Data Valid: The KS8721BL/SL asserts RXDV when it
receives a valid packet. Line operating speed and MII mode will
determine timing changes in the following way:
KS8721BL/SL assigned an MII address between 0 and 31
by the PHYAD inputs.
An internal addressable set of fourteen 16-bit MDIO
registers. Register [0:6] are required and their functions
are specified by the IEEE 802.3 specifications. Additional
registers are provided for expanded functionality.
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KS8721BL/SL Preliminary Rev 0.90
Aug, 2003