KS8721SL-EVAL Micrel Inc, KS8721SL-EVAL Datasheet - Page 22

• Manufacturer Part Number: KS8721SL-EVAL
• Description: BOARD EVAL EXPERIMENT KS8721SL
• Manufacturer: Micrel Inc

Specifications of KS8721SL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8721SL
• Primary Attributes: 1 Port, 100BASE-TX/100BASE-FX/10BASE-T
• Secondary Attributes: MII, RMII, Auto MDI, MDIX, >130 Meter Cable Driver, LDO, IEEE802.3u Compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1010

KS8721BL/SL (3.3V Single Power Supply 10/100BaseTX/FX MII Physical Layer Transceiver)
PLL Clock Synthesizer
Scrambler/De-scrambler (100BaseTX only)
10BaseT Transmit
10BaseT Receive
SQE and Jabber Function (10BaseT only)
The KS8721BL/SL generates 125 M z, 25 M z and 20 M z clocks for
system timing. An internal crystal oscillator circuit provides the
reference clock for the synthesizer.
The purpose of the scrambler is to spread the power spectrum of the
signal in order to reduce EMI and baseline wander.
When TXEN (transmit enable) goes high, data encoding and
transmission will begin. The KS8721BL/SL will continue to encode
and transmit data as long as TXEN remains high. The data
transmission will end when TXEN goes low. The last transition
occurs at the boundary of the bit cell if the last bit is zero, or at the
center of the bit cell if the last bit is one. The output driver is
incorporated into the 100Base driver to allow transmission with the
same magnetics. They are internally wave-shaped and pre-
emphasized into outputs with a typical 2.5 V amplitude. The
harmonic contents are at least 27 dB below the fundamental when
driven by an all-ones Manchester-encoded signal.
On the receive side, input buffer and level detecting squelch circuits
are employed. A differential input receiver circuit and a PLL performs
the decoding function. The Manchester-encoded data stream is
separated into clock signal and NRZ data. A squelch circuit rejects
signals with levels less than 300 mV or with short pulse widths in
order to prevent noises at the RX+ or RX- input from falsely trigger
the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KS8721BL/SL decodes a data
frame. This activates the carrier sense (CRS) ad RXDV signals and
makes the receive data (RXD) available. The receive clock is
maintained active during idle periods in between data reception.
In 10BaseT operation, a short pulse will be put out on the COL pin
after each packet is transmitted. This is required as a test of the
10BaseT transmit/receive path and is called SQE test. The 10BaseT
transmitter will be disabled and COL will go high if TXEN is High for
more than 20 ms (Jabbering). If TXEN then goes low for more than
250 ms, the 10BaseT transmitter will be re-enabled and COL will go
Low.
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KS8721BL/SL Preliminary Rev 0.90
Aug, 2003