EVAL-AD7476ACB Analog Devices Inc, EVAL-AD7476ACB Datasheet - Page 15
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EVAL-AD7476ACB
Manufacturer Part Number
EVAL-AD7476ACB
Description
BOARD EVAL FOR AD7476A
Manufacturer
Analog Devices Inc
Datasheet
1.EVAL-AD7476ACB.pdf
(28 pages)
Specifications of EVAL-AD7476ACB
Rohs Status
RoHS non-compliant
Number Of Adc's
1
Number Of Bits
12
Sampling Rate (per Second)
1M
Data Interface
Serial
Inputs Per Adc
1 Differential
Input Range
0 ~ 5.25 V
Power (typ) @ Conditions
17.5mW @ 1MSPS, 5 V
Voltage Supply Source
Single
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD7476A
Lead Free Status / Rohs Status
Not Compliant
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7476A/AD7477A/AD7478A are fast, micropower,
12-/10-/8-bit, single-supply analog-to-digital converters (ADCs),
respectively. The parts can be operated from a 2.35 V to 5.25 V
supply. When operated from either a 5 V supply or a 3 V supply,
the AD7476A/AD7477A/AD7478A are capable of throughput
rates of 1 MSPS when provided with a 20 MHz clock. The
AD7476A/AD7477A/AD7478A provide the user with an on-
chip, track-and-hold ADC and a serial interface housed in a
tiny 6-lead SC70 or 8-lead MSOP package, offering the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part but also pro-
vides the clock source for the successive-approximation ADC.
The analog input range is 0 V to V
an external reference or an on-chip reference. The reference for
the AD7476A/AD7477A/AD7478A is derived from the power
supply and, thus, gives the widest dynamic input range. The
AD7476A/AD7477A/AD7478A also feature a power-down
option to allow power saving between conversions. The power-
down feature is implemented across the standard serial interface,
as described in the Modes of Operation section.
THE CONVERTER OPERATION
AD7476A/AD7477A/AD7478A are successive approximation,
analog-to-digital converters based around a charge redistribu-
tion DAC. Figure 15 and Figure 16 show simplified schematics
of the ADC. Figure 15 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on V
V
IN
A
SW1
AGND
B
CAPACITOR
SAMPLING
ACQUISITION
PHASE
V
Figure 15. ADC Acquisition Phase
DD
/2
IN
.
SW2
DD
COMPARATOR
. The ADC does not require
REDISTRIBUTION
CHARGE
CONTROL
DAC
LOGIC
Rev. E | Page 15 of 28
When the ADC starts a conversion (see Figure 16), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 17 shows the ADC transfer function.
ADC TRANSFER FUNCTION
The output coding of the AD7476A/AD7477A/AD7478A is
straight binary. The designed code transitions occur at the
successive integer LSB values, that is, 1 LSB, 2 LSB, and so on.
The LSB size is V
AD7477A, and V
characteristic for the AD7476A/AD7477A/AD7478A is shown
in Figure 17.
V
IN
SW1
A
AGND
B
111...111
111...110
111...000
011...111
000...010
000...001
000...000
CAPACITOR
SAMPLING
CONVERSION
Figure 17. AD7476A/AD7477A/AD7478A
PHASE
DD
DD
V
Figure 16. ADC Conversion Phase
DD
0V
AD7476A/AD7477A/AD7478A
/4096 for the AD7476A, V
/256 for the AD7478A. The ideal transfer
/2
1LSB
Transfer Characteristic
ANALOG INPUT
SW2
1LSB = V
1LSB = V
1LSB = V
COMPARATOR
+V
DD
DD
DD
DD
/4096 (AD7476A)
/1024 (AD7477A)
/256 (AD7478A)
– 1LSB
DD
REDISTRIBUTION
/1024 for the
CHARGE
CONTROL
DAC
LOGIC