DEMO9S08EL32AUTO Freescale Semiconductor, DEMO9S08EL32AUTO Datasheet - Page 177
![DEMO BOARD EL32 AUTO](/photos/37/58/375858/demo9s08sg32bd_sml.jpg)
DEMO9S08EL32AUTO
Manufacturer Part Number
DEMO9S08EL32AUTO
Description
DEMO BOARD EL32 AUTO
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheets
1.DEMO9S08EL32.pdf
(356 pages)
2.DEMO9S08EL32.pdf
(14 pages)
3.DEMO9S08EL32.pdf
(2 pages)
Specifications of DEMO9S08EL32AUTO
Contents
Board, Cable, CD and Documentation
Processor To Be Evaluated
MC9S08EL32
Data Bus Width
8 bit
Interface Type
RS-232, USB
Operating Supply Voltage
12 V
For Use With/related Products
MC9S08EL32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.4.1.5
As shown in
signal to terminate the communication. This is used by the master to communicate with another slave or
with the same slave in different mode (transmit/receive mode) without releasing the bus.
11.4.1.6
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or
more masters try to control the bus at the same time, a clock synchronization procedure determines the bus
clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest
one among the masters. The relative priority of the contending masters is determined by a data arbitration
procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The
losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set
by hardware to indicate loss of arbitration.
11.4.1.7
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device’s clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
Freescale Semiconductor
SCL1
SCL2
Figure
SCL
Repeated Start Signal
Arbitration Procedure
Clock Synchronization
11-9, a repeated start signal is a start signal generated without first generating a stop
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Internal Counter Reset
Figure 11-10. IIC Clock Synchronization
Delay
Start Counting High Period
Figure
Inter-Integrated Circuit (S08IICV2)
11-10). When all
177
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