DEMO9S08EL32AUTO Freescale Semiconductor, DEMO9S08EL32AUTO Datasheet - Page 108
![DEMO BOARD EL32 AUTO](/photos/37/58/375858/demo9s08sg32bd_sml.jpg)
DEMO9S08EL32AUTO
Manufacturer Part Number
DEMO9S08EL32AUTO
Description
DEMO BOARD EL32 AUTO
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheets
1.DEMO9S08EL32.pdf
(356 pages)
2.DEMO9S08EL32.pdf
(14 pages)
3.DEMO9S08EL32.pdf
(2 pages)
Specifications of DEMO9S08EL32AUTO
Contents
Board, Cable, CD and Documentation
Processor To Be Evaluated
MC9S08EL32
Data Bus Width
8 bit
Interface Type
RS-232, USB
Operating Supply Voltage
12 V
For Use With/related Products
MC9S08EL32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 7 Central Processor Unit (S08CPUV3)
108
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
MUL
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
NOP
NSA
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
PSHA
PSHH
PSHX
PULA
PULH
PULX
Source
Form
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
(M)
In IX+/DIR and DIR/IX+ Modes,
H:X ← (H:X) + $0001
Unsigned multiply
X:A ← (X) × (A)
Negate
(Two’s Complement) A ← – (A) = $00 – (A)
No Operation — Uses 1 Bus Cycle
Nibble Swap Accumulator
A ← (A[3:0]:A[7:4])
Inclusive OR Accumulator and Memory
A ← (A) | (M)
Push Accumulator onto Stack
Push (A); SP ← (SP) – $0001
Push H (Index Register High) onto Stack
Push (H); SP ← (SP) – $0001
Push X (Index Register Low) onto Stack
Push (X); SP ← (SP) – $0001
Pull Accumulator from Stack
SP ← (SP + $0001); Pull (A)
Pull H (Index Register High) from Stack
SP ← (SP + $0001); Pull (H)
Pull X (Index Register Low) from Stack
SP ← (SP + $0001); Pull (X)
0
C
destination
b7
b7
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
← (M)
Table 7-2. Instruction Set Summary (Sheet 6 of 9)
Operation
source
b0
b0
M ← – (M) = $00 – (M)
X ← – (X) = $00 – (X)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
C
0
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
INH
DIR
INH
INH
IX1
IX
SP1
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
INH
INH
INH
INH
INH
Object Code
9E 68
9E 64
9E 60
9E DA
9E EA
38
48
58
68
78
34
44
54
64
74
4E
5E
6E
7E
42
30
40
50
60
70
9D
62
AA
BA
CA
DA
EA
FA
87
8B
89
86
8A
88
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
5
1
1
5
4
6
5
1
1
5
4
6
5
5
4
5
5
5
1
1
5
4
6
1
1
2
3
4
4
3
3
5
4
2
2
2
3
3
3
rfwpp
p
p
rfwpp
rfwp
prfwpp
rfwpp
p
p
rfwpp
rfwp
prfwpp
rpwpp
rfwpp
pwpp
rfwpp
ffffp
rfwpp
p
p
rfwpp
rfwp
prfwpp
p
p
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
sp
sp
sp
ufp
ufp
ufp
Cyc-by-Cyc
Details
Freescale Semiconductor
V 1 1 H I N Z C
0 1 1 – –
– 1 1 0 – – – 0
– 1 1 – – – – –
– 1 1 – – – – –
0 1 1 – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
– 1 1 – – – – –
1 1 – –
1 1 – – 0
1 1 – –
on CCR
Affect
–
–
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