C8051F360-TB Silicon Laboratories Inc, C8051F360-TB Datasheet - Page 26

• Manufacturer Part Number: C8051F360-TB
• Description: BOARD TARGET/PROTO W/C8051F360
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360-TB

• Contents: Board
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1412

C8051F360/1/2/3/4/5/6/7/8/9
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See Figure 1.8.)
On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the
controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This
allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the
particular application.
1.5.
The C8051F36x Family includes an SMBus/I
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.6.
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three program-
mable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
26
Highest
Priority
Lowest
Priority
Serial Ports
Programmable Counter Array
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
CP0
CP1
PCA
SPI
(P3.0-P3.7)
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
Figure 1.8. Digital Crossbar Diagram (Port 0 to Port 3)
2
4
2
4
7
2
8
8
8
8
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
2
C interface, a full-duplex UART with enhanced baud rate
Rev. 1.0
8
8
8
8
P1MASK, P1MATCH,
P0MASK, P0MATCH
P2MASK, P2MATCH
Registers
Cells
Cells
Cells
Cell
I/O
I/O
I/O
I/O
P0
P1
P2
P3
PnMDIN Registers
PnMDOUT,
3.5–3.7 available on
C8051F360/3
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
C8051F360/1/3/4/6/8
3.1–3.4 available on