C8051F360-TB Silicon Laboratories Inc, C8051F360-TB Datasheet - Page 174

• Manufacturer Part Number: C8051F360-TB
• Description: BOARD TARGET/PROTO W/C8051F360
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360-TB

• Contents: Board
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1412

C8051F360/1/2/3/4/5/6/7/8/9
174
Bits 7–6: RESERVED. Read = 00b. Must Write 00b.
Bits 5–4: CLKDIV1-0: Output SYSCLK Divide Factor.
Bit 3:
Bits 2–0: CLKSL2–0: System Clock Source Select Bits.
SFR Page:
SFR Address:
Reserved Reserved CLKDIV1 CLKDIV0 Reserved CLKSL2
R/W
Bit7
These bits can be used to pre-divide SYSCLK before it is output to a port pin through the
crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
See Section “17. Port Input/Output” on page 183 for more details about routing this output to
a port pin.
RESERVED. Read = 0b. Must Write 0b.
000: SYSCLK derived from the high-frequency Internal Oscillator, and scaled as per the
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the low-frequency Internal Oscillator, and scaled as per the
011: RESERVED.
100: SYSCLK derived from the PLL.
101-11x: RESERVED.
F
0x8F
IFCN bits in OSCICN.
OSCLD bits in OSCLCN.
R/W
Bit6
SFR Definition 16.4. CLKSEL: System Clock Selection
R/W
Bit5
R/W
Bit4
Rev. 1.0
R/W
Bit3
R/W
Bit2
CLKSL1
R/W
Bit1
CLKSL0 00000000
R/W
Bit0
Reset Value