DK-DEV-4SE530N Altera, DK-DEV-4SE530N Datasheet - Page 42

• Manufacturer Part Number: DK-DEV-4SE530N
• Description: KIT DEV STRATIX IV FPGA 4SE530
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SE530N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV E
• Rohs Compliant: Yes
• For Use With/related Products: EP4SE530
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2605

6–16
Figure 6–8. The HSMC Tab
Stratix IV E FPGA Development Kit User Guide
1
You must have the loopback HSMC installed on the HSMC connector that you are
testing for this test to succeed.
The following sections describe the controls on the HSMC tab.
Status
The Status control displays the following status information during the loopback test:
■
■
■
Port
The Port control allows you to specify the type of test to run on the HSMC ports. The
following HSMC port tests are available:
PLL lock—Shows the PLL locked or unlocked state.
Channel lock—Shows the channel locked or unlocked state. When locked, all
lanes are aligned and bonded.
Pattern sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
© May 2010 Altera Corporation
Chapter 6: Board Test System
Using the Board Test System