C8051F326DK Silicon Laboratories Inc, C8051F326DK Datasheet - Page 130
C8051F326DK
Manufacturer Part Number
C8051F326DK
Description
KIT DEV FOR C8051F326/7
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F326DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F326
Silicon Family Name
C8051F32x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F326, C8051F327
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1306
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C8051F326/7
14.1.4. Mode 3: Two 8-bit Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit timers held in TL0 and TH0. The counter in TL0 is
controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can
use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a
timer function sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run con-
trol bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to
generate baud rates for the UART. While Timer 0 is operating in Mode 3, Timer 1 run control is handled
through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To
disable Timer 1, configure it for Mode 3.
130
G
A
T
E
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
Pre-scaled Clock
SYSCLK
GATE0
/INT0
Figure 14.3. T0 Mode 3 Block Diagram
CKCON
M
T
1
TR0
M
T
0
0
1
S
C
A
1
S
C
A
0
Rev. 1.1
TR1
(8 bits)
(8 bits)
TH0
TL0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
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