C8051F326DK Silicon Laboratories Inc, C8051F326DK Datasheet - Page 112

• Manufacturer Part Number: C8051F326DK
• Description: KIT DEV FOR C8051F326/7
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F326DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F326/F327
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F326
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F326, C8051F327
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1306

C8051F326/7
12.13. Controlling Endpoint1 OUT
Endpoint1 OUT is managed via USB registers EOUTCSRL and EOUTCSRH. It can be used for Interrupt,
Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in register
EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1 OUT interrupt may be generated by the following:
12.13.1.Endpoint1 OUT Interrupt or Bulk Mode
When the ISO bit (EOUTCSRH.6) is logic 0, Endpoint1 operates in Bulk or Interrupt mode. Once it has
been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0
SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to ‘1’ and generate an
interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data
packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL reg-
isters. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset
the OPRDY bit to ‘0’.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While
SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware gen-
erates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The
STSTL bit must be reset to ‘0’ by firmware.
Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buff-
ering is enabled for Endpoint1, it is possible for two packets to be ready in the OUT FIFO at a time. In this
case, hardware will set OPRDY to ‘1’ immediately after firmware unloads the first packet and resets
OPRDY to ‘0’. A second interrupt will be generated in this case.
12.13.2.Endpoint1 OUT Isochronous Mode
When the ISO bit (EOUTCSRH.6) is set to ‘1’, Endpoint1 operates in Isochronous (ISO) mode. Once it has
been configured for ISO OUT mode, the host will send exactly one data per USB frame; the location of the
data packet within each frame may vary, however. Because of this, it is recommended that double buffer-
ing be enabled when Endpoint1 is used in Isochronous mode.
Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO,
set the OPRDY bit (EOUTCSRL.0) to ‘1’, and generate an interrupt (if enabled). Firmware would typically
use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to ‘0’.
If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and
the OVRUN bit (EOUTCSRL.2) set to ‘1’. If USB0 receives an ISO data packet with a CRC error, the data
packet will be loaded into the endpoint FIFO, OPRDY will be set to ‘1’, an interrupt (if enabled) will be gen-
erated, and the DATAERR bit (EOUTCSRL.3) will be set to ‘1’. Software should check the DATAERR bit
each time a data packet is unloaded from an ISO OUT endpoint FIFO.
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1. Hardware sets the OPRDY bit (EINCSRL.0) to ‘1’.
2. Hardware generates a STALL condition.
Rev. 1.1