OM11048 NXP Semiconductors, OM11048 Datasheet - Page 27

• Manufacturer Part Number: OM11048
• Description: BOARD LPCXPRESSO LPC1343
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor
• Type: MCUr

Specifications of OM11048

• Contents: Board, Software
• Processor To Be Evaluated: LPC1343
• Processor Series: LPC13xx
• Interface Type: USB, I2C, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Tool Type: Demonstration Board
• Core Architecture: ARM
• Cpu Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LPC1343
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4947

NXP Semiconductors
LPC1311_13_42_43
Product data sheet
7.18.5 Boot loader
7.18.6 APB interface
7.18.7 AHB-Lite
7.18.8 External interrupt inputs
7.18.9 Memory mapping control
7.19 Emulation and debugging
The boot loader controls initial operation after reset and also provides the means to
program the flash memory. This could be initial programming of a blank device, erasure
and re-programming of a previously programmed device, or programming of the flash
memory by the application program in a running system.
The boot loader code is executed every time the part is reset or powered up. The loader
can either execute the ISP command handler or the user application code, or, on the
LPC134x, it can program the flash image via an attached MSC device through USB
(Windows operating system only). A LOW level during reset applied to the PIO0_1 pin is
considered as an external hardware request to start the ISP command handler or the USB
device enumeration. The state of PIO0_3 determines whether the UART or USB interface
will be used (LPC134x only).
The APB peripherals are located on one APB bus.
The AHB-Lite connects the instruction (I-code) and data (D-code) CPU buses of the ARM
Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 256 word boundary.
Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 August 2010
Section
7.18.1).
32-bit ARM Cortex-M3 microcontroller
LPC1311/13/42/43
© NXP B.V. 2010. All rights reserved.
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