AT91SAM9260-EK Atmel, AT91SAM9260-EK Datasheet - Page 22

• Manufacturer Part Number: AT91SAM9260-EK
• Description: KIT EVAL FOR AT91SAM9260
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9260-EK

• Contents: Evaluation Board, Parallel Cable and CD-ROM
• Processor To Be Evaluated: AT91SAM9260
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• Core: ARM 9
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Silicon Core Number: AT91SAM9260
• Silicon Family Name: ARM
• Kit Contents: Board, Cables, CD, Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.1.1
8.1.1.2
8.2
8.2.1
22
External Memories
AT91SAM9260
External Bus Interface
BMS = 1, Boot on Embedded ROM
BMS = 0, Boot on External Memory
The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin
at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved
for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
The system boots using the Boot Program.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
The external memories are accessed through the External Bus Interface. Each Chip Select line
has a 256-Mbyte memory area assigned.
Refer to the memory map in
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
• SAM-BA
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
4. Switch the main clock to the new value.
• Integrates three External Memory Controllers
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
– SPI DataFlash
– 8-bit and/or 16-bit NAND Flash
– Serial communication on a DBGU
– USB Device Port
to the new clock.
– Static Memory Controller
– SDRAM Controller
®
Monitor in case no valid program is detected in external NVM, supporting
®
connected on NPCS0 and NPCS1 of the SPI0
Figure 8-1 on page
20.
6221JS–ATARM–17-Jul-09