AT91SAM9260-EK Atmel, AT91SAM9260-EK Datasheet - Page 16

• Manufacturer Part Number: AT91SAM9260-EK
• Description: KIT EVAL FOR AT91SAM9260
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9260-EK

• Contents: Evaluation Board, Parallel Cable and CD-ROM
• Processor To Be Evaluated: AT91SAM9260
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• Core: ARM 9
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Silicon Core Number: AT91SAM9260
• Silicon Family Name: ARM
• Kit Contents: Board, Cables, CD, Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
16
Bus Matrix
AT91SAM9260
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
• 8-Kbyte Data Cache, 8-Kbyte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
each quarter of the page
system flexibility
32-bit data interface
(Words)
or fixed default master
internal boot, one for external boot, one after remap
6221JS–ATARM–17-Jul-09