ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 755
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
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36. Timer Counter (TC)
36.1
36.2
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Description
Embedded Characteristics
The Timer Counter (TC) includes 9 identical 16-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including
frequency measurement, event counting, interval measurement, pulse generation, delay timing
and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose
input/output signals which can be configured by the user. Each channel drives an internal inter-
rupt signal which can be programmed to generate processor interrupts.
The Timer Counter (TC) embeds a quadrature decoder logic connected in front of the timers and
driven by TIOA0, TIOB0 and TIOA1 inputs. When enabled, the quadrature decoder performs the
input lines filtering, decoding of quadrature signals and connects to the timers/counters in order
to read the position and speed of the motor through the user interface.
The Timer Counter block has two global registers which act upon all TC channels.
The Block Control Register allows the channels to be started simultaneously with the same
instruction.
The Block Mode Register defines the external clock inputs for each channel, allowing them to be
chained.
Table 36-1
Counter 0 to 2.
Table 36-1.
Note:
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
• Provides 9 16-bit Timer Counter channels
• Wide range of functions including:
– Frequency measurement
– Event counting
– Interval measurement
– Pulse generation
– Delay timing
– Pulse Width Modulation
– Up/down capabilities
1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master CLock Register),
TIMER_CLOCK5 input is Master Clock, i.e., Slow CLock modified by PRES and MDIV fields.
gives the assignment of the device Timer Counter clock inputs common to Timer
Timer Counter Clock Assignment
(1)
Definition
MCK/2
MCK/8
MCK/32
MCK/128
SLCK
SAM3U Series
SAM3U Series
755
755
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