ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 178

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.19.9
13.19.9.1
178
SAM3U Series
Level-sensitive interrupts
Hardware and software control of interrupts
The processor supports level-sensitive interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typ-
ically this happens because the ISR accesses the peripheral, causing it to clear the interrupt
request.
When the processor enters the ISR, it automatically removes the pending state from the inter-
rupt, see
signal is not deasserted before the processor returns from the ISR, the interrupt becomes pend-
ing again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the fol-
lowing reasons:
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pend-
ing to active. Then:
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
• the NVIC detects that the interrupt signal is HIGH and the interrupt is not active
• the NVIC detects a rising edge on the interrupt signal
• software writes to the corresponding interrupt set-pending register bit, see
• Software writes to the corresponding interrupt clear-pending register bit.
pending Registers” on page
Trigger Interrupt Register” on page
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
– If the interrupt signal is not pulsed while the processor is in the ISR, when the
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
processor returns from the ISR the state of the interrupt changes to inactive.
“Hardware and software control of
171, or to the STIR to make an SGI pending, see
177.
interrupts”. For a level-sensitive interrupt, if the
6430D–ATARM–25-Mar-11
“Interrupt Set-
“Software