LM3528TMEV National Semiconductor, LM3528TMEV Datasheet - Page 29

• Manufacturer Part Number: LM3528TMEV
• Description: BOARD EVAL FOR LM3528 12MCRSMD
• Manufacturer: National Semiconductor

Specifications of LM3528TMEV

• Current - Output / Channel: 20mA
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 21V
• Features: Dimmable, I²C Interface
• Voltage - Input: 2.5 ~ 5.5V
• Utilized Ic / Part: LM3528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATION CIRCUITS
LAYOUT CONSIDERATIONS
Refer to AN-1112 for µSMD package soldering
The high switching frequencies and large peak currents in the
LM3528 make the PCB layout a critical part of the design. The
proceeding steps should be followed to ensure stable opera-
tion and proper current source regulation.
1, C
device as possible. The input capacitor supplies the driver
currents during MOSFET switching and can have relatively
large spikes. Connecting the capacitor close to the device will
reduce the inductance between CIN and the LM3528 and
eliminate much of the noise that can disturb the internal ana-
log circuitry.
2, Connect the anode of the Schottky diode as close to the
SW pin as possible. This reduces the inductance between the
internal MOSFET and the diode and minimizes the noise gen-
erated from the discontinuous diode current and the PCB
trace inductance that will add ringing at the SW node and filter
through to VOUT. This is especially important in VOUT mode
when designing for a stable output voltage.
3, C
trace lengths between the diode and PGND. Connect the
positive terminal of the output capacitor (COUT+) as close as
possible to the cathode of the diode. Connect the negative
terminal of the output capacitor (COUT-) as close as possible
FIGURE 19. LED Backlight + OLED Power Supply
IN
OUT
should be located on the top layer and as close to the
should be located on the top layer to minimize the
29
to the PGND pin on the LM3528. This minimizes the induc-
tance in series with the output capacitor and reduces the
noise present at VOUT and at the PGND connection. This is
important due to the large di/dt into and out of COUT. The
returns for both CIN and COUT should terminate directly to
the PGND pin.
4, Connect the inductor on the top layer close to the SW pin.
There should be a low impedance connection from the induc-
tor to SW due to the large DC inductor current, and at the
same time the area occupied by the SW node should be small
so as to reduce the capacitive coupling of the high dV/dt
present at SW that can couple into nearby traces.
5, Route the traces for R
from the SW node to minimize the capacitance between these
nodes that can couple the high dV/dt present at SW into them.
Furthermore, the feedback divider and R
icated returns that terminate directly to the PGND pin of the
device. This will minimize any shared current with COUT or
CIN that can lead to instability. Avoide routing the SUB/FB
node close to other traces that can see high dV/dt such as the
I2C pins. The capacitive coupling on the PCB between FB
and these nodes can disturb the output voltage and cause
large voltage spikes at VOUT.
6, Do not connect any external capacitance to the SET pin.
7, Refer to the LM3528 Evaluation Board as a guide for proper
layout.
SET
and the feedback divider away
SET
should have ded-
30020561
www.national.com