LM3528TMEV National Semiconductor, LM3528TMEV Datasheet - Page 16

• Manufacturer Part Number: LM3528TMEV
• Description: BOARD EVAL FOR LM3528 12MCRSMD
• Manufacturer: National Semiconductor

Specifications of LM3528TMEV

• Current - Output / Channel: 20mA
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 21V
• Features: Dimmable, I²C Interface
• Voltage - Input: 2.5 ~ 5.5V
• Utilized Ic / Part: LM3528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
Figures 12 - 15). Figure 16 details an example of a 32 bit pat-
tern at a specific programmed duty cycle and frequency. A ‘1’
written to the PGEN_ registers forces HWEN/PGEN/GPIO
low. A ‘0’ causes HWEN/PGEN/GPIO to go open drain.
Bits <5:3> in the HPG register have three functions; GPIO
enable, duty cycle select, and pattern latch. Any combination
of these bits other than ‘000’ or ’111’ puts HWEN/PGEN/GPIO
into PGEN mode at the specified duty cycle shown in Table
6. Writing a ‘111’ to bits <5:3> latches the 32 bit pattern pro-
grammed into the 4 pattern generator registers PGEN0,
PGEN1, PGEN2, PGEN3 into the internal shift register. When
bits <5:3> = ‘000’ the PGEN mode is off and HWEN/PGEN/
GPIO is configured as a GPIO.
Bits <7:6> of the HPG register control the pattern frequency.
See Table 6 for the detailed breakdown of each available fre-
quency. Figure 16 details the pattern programming and figure
17 shows the pattern output at HWEN/PGEN/GPIO.
GENERAL PURPOSE I/O (GPIO1)
With bits <5:3> and bit 0 of the HPG register all set to ‘0’
HWEN/PGEN/GPIO functions as an open drain General Pur-
pose I/O. In this mode, bit 1 of the HPG register controls the
logic direction (Input or Output) and bit 2 holds the logic data.
With bit 1 set to ‘0’ HWEN/PGEN/GPIO is configured as an
output. In this mode a ‘0’ written to bit 2 forces HWEN/PGEN/
GPIO to logic low. Likewise, a ‘1’ written to bit 2 will force
HWEN/PGEN/GPIO open drain. When bit 1 is set to ‘1’
HWEN/PGEN/GPIO is configured as a logic input. In this
mode when HWEN/PGEN/GPIO is externally pulled low a ‘0’
is written to bit 2 of the HPG register. Likewise, when HWEN/
PGEN/GPIO is externally pulled high a ‘1’ is written to bit 2 of
the HPG register. Table 6 and Figure 10 detail the bit functions
16
of the HPG register and their power-on-reset values. Note that
the logic output levels for the GPIO function of this pin are
inverted compared to the PGEN functions. For example, a 1
written to the PGEN registers cause the HWEN/PGEN/GPIO
pin to pull low while a 1 written to the bit 2 of the HPG register
causes the pin to go open drain.
GENERAL PURPOSE I/O (GPIO0)
The GPIO pin is a dedicated General Purpose I/O (open
drain) and is controlled via the GPIO register at address 0x81.
Bit 1 holds the logic data while bit 0 controls the logic direction
(Input or Output). Bits <7:2> are un-used and will always read
back as logic '1'. With bit 0 set to ‘0’ GPIO is configured as an
output. In this mode a ‘0’ written to bit 1 forces GPIO to a logic
low. Likewise, a ‘1’ written to bit 1 will force GPIO to logic high.
When bit 0 is set to ‘1’ GPIO is configured as a logic input. In
this mode when GPIO is externally pulled low a ‘0’ is written
to bit 1 of the GPIO register. Likewise, when GPIO is exter-
nally pulled high a ‘1’ is written to bit 2 of the HPG register.
Table 7 and Figure 11 detail the bit functions and power-on-
reset values of GPIO.
During an initial GPIO write two I2C sequences (Slave I.D,
Register Address, Register Data) are required to change the
state of the GPIO pin. The first write configures the GPIO pin
as an output. The second write will change the state of the
GPIO output to the desired logic '1' or '0'.
THERMAL SHUTDOWN
The LM3528 offers a thermal shutdown protection. When the
die temperature reaches +140°C the device will shutdown
and not turn on again until the die temperature falls below
+120°C.