LM3528TMEV National Semiconductor, LM3528TMEV Datasheet - Page 22

• Manufacturer Part Number: LM3528TMEV
• Description: BOARD EVAL FOR LM3528 12MCRSMD
• Manufacturer: National Semiconductor

Specifications of LM3528TMEV

• Current - Output / Channel: 20mA
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 21V
• Features: Dimmable, I²C Interface
• Voltage - Input: 2.5 ~ 5.5V
• Utilized Ic / Part: LM3528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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TABLE 6. HPG Register Function
Note 1: This represents the amount of time each programmed
bit will be present at HWEN/PGEN/GPIO. The entire pattern
period will be 32 × Bit Period.
Note 2: This duty cycle indicates the fraction of time the pat-
tern is being output at HWEN/PGEN/GPIO. For example the
1/2 duty cycle (bits <5:3> = 010) will have the 32 bit pattern
X
00 = 1.6µs/
bit (625kHz)
01 = 26ms/
bit (38Hz)
10 = 52ms/
bit (19Hz)
11 = 105ms/
bit (9.5Hz)
Note 1
X
X
(PGEN Bit
Bits 7 – 6
Period)
X
001 = 100%
010 = 1/2
011 = 1/3
100 = 1/4
101 = 1/6
110 = 1/12
111 = Latch Pat-
tern Into Shift Reg-
ister
Note 2
000
000
Bits 5 - 3 (PGEN
and Duty Cycle
Enable/Disable
Selection)
X
X
GPIO Read
Data
GPIO Write
Data
Bit 2 (GPIO
Data)
FIGURE 10. HPG Register Description
X
X
1
0
Bit 1 (GPIO
Direction)
Data
22
0
1
1
1
Bit 0 (HWEN
output once followed by a dead time (HWEN/PGEN/GPIO
high impedance) equal to 1×’s the pattern period (Deadtime
= 32 × Bit_Period × (1/DutyCycle -1). For the 100% duty cycle
setting the 32 bit pattern will repeat constantly with no dead-
time.
Control)
HWEN/PGEN/GPIO is configured as an
active high Hardware Enable Input (HWEN)
HWEN/PGEN/GPIO is configured as a
Pattern Generator Output with the frequency
set by bits <7:6> and the duty cycle set by bits
<5:3>. (See Figure 11.)
HWEN/PGEN/GPIO is configured as a GPIO
Input. Read data from bit 2.
HWEN/PGEN/GPIO is configured as a GPIO
Output. A ‘1’ written to bit 2 will force HWEN/
PGEN/GPIO high; a 0 written to bit 2 will force
HWEN/PGEN/GPIO low.
Function
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